DP83858VF datasheet(20/37 Pages) NSC

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4.11 Port Management Counter Registers

Each of the 8 ports of the DP83858 has a set of 4 event

counters whose values can be read or pre-set (written)

through the Port Management Counter Registers. Ports 0

through 5 have their registers in register page 0 and ports 6

and 7 in register page 1.

All counters will rollover to zero after reaching their maxi-

mum count: they are not "sticky". There is no interrupt on

reaching maximum count, so the management software

must ensure the registers are polled often enough so as

not to rollover twice; management software can deduce a

single rollover as long as the counter has not yet reached

the previously read value (a simple compare). It is safest

for the management software to guarantee to check all

counters at least once per possible rollover time. All

counters are cleared to zero at power-on and/or reset

(/RST asserted).

The Short Event, Late Event and Collision Counters are

32-bits long. Since the corresponding Counter Registers

are only 16-bits, the DP83858 has to internally multiplex

the counter value into two 16-bit values that the manage-

ment software must then concatenate to form the full 32-bit

value. Some restrictions apply to the access of the counter

registers:

1. A 32-bit counter must be read as two consecutive 16-

bit accesses. Upon the first access, the DP83858 plac-

es the full 32-bit counter value in a holding register,

from where it transfers the upper 16 bits first. The sec-

ond access reads the lower 16 bits of the counter. If

there is any access to another register in between the

counter reads, the concatenated value of the counter

will be invalid (the DP83858's internal multiplexer will

reset).

2. For the same reason, a 32-bit counter must be written

as two consecutive 16-bit accesses.

3. All counters are cleared by writing 0000 0000h to them.

The counter value is unaffected by read accesses.

4. The counters should only be written to when they are

disabled. This is done by deasserting the MGTEN bit in

the CONFIG register.

4.11.1 Short Event Counter Registers

Per port ('n' = port number) counters that indicate the num-

ber of Carrier Events that were active for less than the

ShortEventMaxTime, which is deﬁned as between 74 and

82 (76 nominal) bit times.

4.11.2 Late Event Counter Registers

Per port ('n' = port number) counters that indicate the num-

ber of collisions that occurred after the LateEventThresh-

old, which is deﬁned to be 480 to 565 bit times (512

nominal). Both the Late Event and Collision Counters will

be incremented when this event occurs.

4.11.3 Collision Counter Registers

Per port ('n' = port number) counters that indicate the num-

ber of collisions (COL asserted).

4.11.4 Auto-Partition Counter Registers

Per port ('n' = port number) counters that indicate the num-

ber of times the port was auto-partitioned.

4.12 Silicon Revision Register (SIREV)

Bit

Access

Bit Description

D15 - D0

r/w

First access - most significant word of

P'n'_SE

Second access - least significant word

of P'n'_SE

Bit

Access

Bit Description

D15 - D0

r/w

First access - most significant word of

P'n'_LE

Second access - least significant word

of P'n'_LE

Bit

Access

Bit Description

D15 - D0

r/w

First access - most significant word of

P'n'_COL

Second access - least significant word

of P'n'_COL

Bit

Access

Bit Description

D15 - D0

r/w

P'n'_PART

Page 1

Address 4h

Bit

Bit Name

Access

Bit Description

D15 - D0 SI_REV[15:0]

read

only

Silicon revision - cur-

rently reads all 0's.

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