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DP83858VF Datasheet(PDF) 17 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83858VF
Description  100 Mb/s TX/T4 Repeater Interface Controller (100RIC8??
PDF  37 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83858VF Datasheet(HTML) 17 Page - National Semiconductor (TI)

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4.3 Configuration Register (CONFIG)
Page 0
Address 0h
Page 1
Address 0h
Bit
Bit Name
Access
Bit Description
D15 - D6
reserved
—
For compatibility with future enhanced versions these bits must be written as zero.
They are undefined when read.
D5
REGEN_PRE
r/w
Regenerate Preamble: This bit may be used to overwrite/change the repeater mode
(TX or T4) that is set by the MODE[1:0] pins at power-up. If MODE[1:0] is 1, 1 then
this bit is set, otherwise this bit will be zero.
The time when the preamble is regenerated depends upon the type of the PHY (ei-
ther TX or T4 PHYs) attached to the repeater. For a TX PHY, preamble is regenerat-
ed approximately 4 clocks (RXC) after the /IR_ACTIVE assertion, and for a T4 PHY,
preamble is regenerated approximately 12 clocks after the /IR_ACTIVE assertion.
D4
MGTEN
r/w
Management Enable: This bit enables all the management counters.
0:
Management Counters disabled (default).
1:
Management Counters enabled.
Note: The management counters can only be reliably written to when they are dis-
abled.
D3
COL_LIMIT32
r/w
This bit configures the collision limit for Auto-Partitioning algorithm:
0:
Consecutive Collision Limit set to 64 consecutive collisions (default). A port will
be partitioned on the 65th consecutive collision.
1:
Consecutive Collision Limit set to 32 consecutive collisions. A port will be parti-
tioned on the 33rd consecutive collision.
D2
DIS_PART
r/w
This bit disables the Auto-Partitioning algorithm:
0:
Auto-Partitioning is not disabled (default).
1:
Auto-Partitioning is disabled.
D1
PHY_ACCESS
r/w
This bit allows the management agent to access the DP83840A PHY chip’s register
via the MII serial protocol.
0:
PHY access disabled (default).
1:
PHY register access enabled.
Note: When in PHY_access mode, RDIO will be driven by the DP83858 during the
read phase for all read commands. This is to allow the DP83840A Physical Layer de-
vices to pass their data through their local DP83858. While in this mode, contention
will result (on the RDIO line) if any device other than this DP83858 or the DP83840A
Physical Layer devices are accessed.
D0
RST_RSM
r/w
Setting this bit holds the Repeater State Machines in reset. The management event
flags and counters are unaffected by this bit. Setting this bit while a reception is in
progress may truncate the packet.
0:
DP83858 in normal operation (default).
1:
DP83858 held in reset.



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