DP83858VF datasheet(15/37 Pages) NSC

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This preamble only needs to be sent once (at reset). From

then on, the <start> ﬁeld lets the receive logic know where

the beginning of the data frame occurs.

To access the Physical Layer devices via the serial bus, the

DP83858 has a “phy_access” mode. When in this mode,

the register data input/output (RDIO) is gated to the

GRDIO pin. This signal is connected to the serial data pins

of the Physical Layer devices.

In this mode the buffers which drive RDIO and GRDIO will

turn on in the appropriate direction for each serial access.

In order to avoid possible contention problems, the user

must ensure that only one DP83858 at a time has the

"phy_access" bit set. The CONFIG register contains the

“phy_access” bit, which can be set or cleared at any time.

Figure 3 shows a possible system implementation of the

RDIO/GRDIO connection scheme. In this example, the

DP83858 with address 00001 has its "phy_access" bit set,

allowing its eight DP83840A PHY devices to be accessed

by the DP83856 100RIB.

MII serial management contention problems can be

avoided by keeping to the addressing convention shown in

Figure 3.

3.12 Jabber/Partition LED Driver Logic

This logic encodes the current auto-partition status (from

the PARTITION register) and the jabber status (from the

JABBER

and

outputs

this

information

PART[5:0] pins. PART[3:0] cycles through each port num-

ber and PART[5:4] indicates the port’s status. PART[5] indi-

cates the Jabber status for each port (0 = LED OFF, 1

=LED ON - Port Jabbering). PART[4] indicates the Partition

status for each port (0 = LED OFF, 1 = LED ON - Port Auto-

Partitioned).

The port number on PART[3:0] is cycled with a 25MHz.

External logic is required to decode the PART[5:0] outputs

and drive the Partition and Jabber LEDs. Multi-color LEDs

could be driven with the appropriate logic if required.

One possible implementation of a DP83858 Port Partition

and Jabber Status LED scheme is given in section 5.5.

3.13 EEPROM Serial Read Access

After reset is de-asserted, the DP83858 will serially read

an NM93C06 EEPROM (or equivalent). Only the ﬁrst 32-

bits starting from address 0 will be read. Write access is

not provided. The data is written to registers HUBID0 and

HUBID1. The ﬁrst bit read is written to HUBID0[0]; the last

bit read will be written to HUBID1[15].

The DP83858 EEPROM interface implements the serial

protocol as shown in Figure 3. The DP83858 will issue two

read commands to obtain the 32-bit ID. The serial clock,

EE_CK will be continuous. For more explicit timing dia-

grams please refer to the NM93C06 datasheet.

The NM93C06 EEPROM must be pre-programmed with

the HUBID value prior to ﬁtting the device to the circuit

since the DP83858 does not support programming of this

device in circuit.

Table 1. Serial Register Interface Encoding

Field

Encoding

Description

<start>

Indicates the beginning of an opcode operation.

Read

Write

all others

Reserved

00000 - 11111 Five bits are provided to address up to 32 16-bit registers.

<device addr> 00000 - 11111 Five bits are provided to address up to 32 devices.

Figure 4. Serial EEPROM Access Protocol

EE_CS

<1...10><00000><1...>

<1...0><00001><1...>

<0><D15..D0>

EE_DI

EE_DO

<0><D31..D16>

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