REV. 0

–24–

AD1980

JS0INT

Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR

should clear this bit by writing a “0” to it. Note that the interrupt to the system is actually an OR combination of

this bit and JS1INT. Also, note that the actual interrupt implementation is selected by the INTS bit (Register 76h).

It is also possible to generate a software system interrupt by writing a “1” to this bit.

JS1INT

Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR

should clear this bit by writing a “0” to it. See the JS0INT description for additional details.

JS0ST

JS0 STATE. This bit always reports the logic state of JS0 pin.

JS1ST

JS1 STATE. This bit always reports the logic state of JS1 pin.

JS0MD

JS0 Mode. This bit selects the operation mode for the JS0 pin.

0 = Jack Sense Mode (reset default)

1 = Interrupt Mode

JS1MD

JS1 Mode. This bit selects the operation mode for the JS1 pin.

0 = Jack Sense Mode (reset default)

1 = Interrupt Mode

JS0TMR

JS0 Timer Enable. If this bit is set to a “1,” JS0 must be high for greater than 278 ms to be recognized.

JS1TMR

JS1 Timer Enable. If this bit is set to a “1,” JS1 must be high for greater than 278 ms to be recognized.

JS0EQB

JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to “1,” JS0 = 1 will

cause the EQ to be bypassed.

JS1EQB

JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to “1,” JS1 = 1 will

cause the EQ to be bypassed.

JSMT[2,0]

JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table IX).

JS0DMX

JS0 Down = Mix Control Enable. This bit enables JS0 to control the Down-Mix function. This function allows a

digital mix of six channels of audio into 2-channel audio. The mix can then be routed to the stereo Line_out or

HP_out jacks. When this bit is set to “1,” JS0 = 1 will activate the Down-Mix conversion.

See the DMIX description in Register 76h. The DMIX bits select the Down-Mix implementation type and can also

force the function to be activated.

JS1DMX

JS1 Down Mix Control Enable. This bit enables 2-channel to 6-channel audio Spread function when both Jack

Senses are active (logic state “1”).

Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses. See this bit’s

description in Register 76h for a better understanding of the Spread function.

JSSPRD

JS Spread Control Enable. This bit enables 2-channel to 6-channel audio Spread function when both Jack Senses

are active (logic state “1”).

Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses. See this bit’s

description in Register 76h for a better understanding of the Spread function.

Jack Sense/Audio Interrupt Status Register (Index 72h)

Reg

No. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

72h

Jack

JS1

JS1

JS0

JS

JS

JS

JS1

JS0

JS1

JS0

JS1

JS0

JS1

JS0

JS1

JS0

0000h

Sense

SPRD DMX

DMX

MT2

MT1

MT0

EQB

EQB

TMR

TMR

MD

MD

ST

ST

INT

INT

All register bits are read/write except for JS0ST and JS1ST, which are read only.

EQ Data Register (Index 62h)

Reg

No. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h

This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the

BCA Bits in the EQ CNTRL register (60h). Data will only be written to memory if the EQM bit (Register 60h, Bit 15) is asserted.

CFD[15,0]

Coefficient Data. The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is

the MSB and the CFD0 bit is the LSB.