DP83905AVQB datasheet(63/80 Pages) NSC

63 / 80 page

60 Operation of ATLANTIC Controller (Continued)

16-Bit Shared Memory Mode Write Bus Timing with DWID High

TLF11498 – 46

This is the type of cycle used to write 16 bits to buffer RAM in shared memory mode when DWID is high These accesses are

entirely asynchronous with the ATLANTIC Controller responding when it decodes the correct address on LA17 – 23 SA0 – 19

and a MWR If AEN is high the cycle will be ignored CHRDY is deasserted if the ATLANTIC Controller is not ready to respond

and asserted when ready If it is ready immediately CHRDY is not deasserted The 816-bit in Control Register 2 must be set to

allow generation of M16 This will be generated whenever the LA17 – 23 lines match the corresponding values in Control

Register 2 It will therefore be generated for a full 128 kbytes of address space although the ATLANTIC Controller will occupy

less than that It may be preferable to only set the 816-bit for the duration of a transfer to the buffer RAM The ATLANTIC

Controller will also compare the address line programmed in Control Register 1 before allowing accesses to buffer RAM and

therefore do a complete decode The system indicates that this is a 16-bit transfer by asserting SBHE and accessing an even

address SA0 low The full 16 bits of data bus are used on both system and memory support busses

DP83905AVQB Datasheet(PDF) 63 Page - National Semiconductor (TI)