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DP83905AVQB Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83905AVQB
Description  AT Local Area Network Twisted-Pair Interface Controller
PDF  80 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83905AVQB Datasheet(HTML) 11 Page - National Semiconductor (TI)

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40 Functional Description (Continued)
16-BIT IO PORT COMPATIBLE MODE IO ADDRESS
MAPPING
This mode is compatible with Novell’s NE2000 The base
IO address of the ATLANTIC Controller is configured by
Configuration Register A (either upon power up or by soft-
ware writing to this register) At that address the following
structure appears
Base a 00H
DP8390
Core
Registers
Base a 0FH
Base a 10H
Data Transfer Port
Base a 17H
Base a 18H
Reset Port
Base a 1FH
FIGURE 5 IO Port Mode Register IO Map
The registers within this area are 8 bits wide but the data
transfer port is 16 bits wide The ATLANTIC Controller’s
registers can be programmed to control the passing of data
between its internal memory and the data transfer port By
accessing the data transfer port (using IO instructions) the
user can transfer data to or from the ATLANTIC Control-
ler’s internal memory The ATLANTIC Controller’s internal
memory map is as shown in
Figure 6
ATLANTIC Controller actually has a 64k address range but
only does partial decoding on these devices The PROM
data is mirrored at all decodes up to 4000H and the entire
map is repeated at 8000H To access either the PROM or
the RAM the user must initiate a Remote DMA transfer be-
tween the IO port and memory
On a remote read the ATLANTIC Controller moves data
from its internal memory map to the IO port and the host
system reads it by using an ‘‘INW’’ or ‘‘INSW’’ instruction
from the IO address of the data transfer port If the system
attempts to read the port before ATLANTIC Controller has
written the next word of data to it ATLANTIC Controller will
insert wait states into the system cycle using the CHRDY
0000H
D15
D0
001FH
PROM
Aliased PROM
4000H
8kx16
Buffer RAM
7FFFH
8000H
Aliased PROM
C000H
Aliased
Buffer RAM
FFFFH
(a)
D15
D0
1EH
00
57H
1CH
00
57H

00
RESERVED

0AH
00
E’net Address 5
08H
00
E’net Address 4
06H
00
E’net Address 3
04H
00
E’net Address 2
02H
00
E’net Address 1
00H
00
E’net Address 0
(b)
FIGURE 6 a) NIC Core’s Memory Map
b) 16-Bit Prom Map
11



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