DP83905AVQB datasheet(68/80 Pages) NSC

68 / 80 page

60 Operation of ATLANTIC Controller (Continued)

RAM Access Timing

Memory Support Read

TLF11498 – 51

This is a memory read cycle executed by the ATLANTIC Controller’s internal DMA This is used to either load the data transfer

port during a Remote Read in IO mode or to load the FIFO for a transmission on the network in both modes This transfer is

synchronized to BSCLK which can be either driven from the 20 MHz input on X1 or by the BSCLK input This is selected by the

CLKSEL bit in Configuration Register C If there is 8 kbytes of RAM only RCS1 is used if 16 kbytes are available RCS1 and

RCS2 are used

Memory Support Write

TLF11498 – 52

This is a memory write cycle executed by the ATLANTIC Controller’s internal DMA This is used to either write from the data

transfer port during a Remote Write in IO mode or to empty the FIFO during a reception from the network in both modes This

transfer is synchronized to BSCLK which can be either driven from the 20 MHz input on X1 or by the BSCLK input This is

selected by the CLKSEL bit in Configuration Register C If there is 8 kbytes of RAM only RCS1 is used if 16 kbytes are available

RCS1 and RCS2 are used

DP83905AVQB Datasheet(PDF) 68 Page - National Semiconductor (TI)