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DP83905AVQB Datasheet(PDF) 79 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83905AVQB
Description  AT Local Area Network Twisted-Pair Interface Controller
PDF  80 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83905AVQB Datasheet(HTML) 79 Page - National Semiconductor (TI)

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90 AC Timing Test Conditions
Input Pulse Levels (TTLCMOS)
GND to 30V
Input Rise and Fall Times (TTLCMOS)
5 ns
Input and Output Reference Levels
13V
(TTLCMOS)
Input Pulse Levels (Diff)
b
350 mV to b1315 mV
Input and Output
50% Point of
Reference Levels (Diff)
the Differential
TRI-STATE Reference Levels
Float (DV) g05V
Output Load (See Figure Below)
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at the
AUI side of the pulse transformer
Output Load
(See Figure Below)
TLF11498 – 61
Note 1
Load Capacitance used depends on output type (includes scope
and jig capacitance)
For 3SL MOS TPI AUI CL e 50 pF
For 3SH OCH CL e 240 pF
Note 2
Specifications which measure delays from an active state to a high
impedance state are not guaranteed by production test but are character-
ized using 70 pF and are correlated to determine true driver turn-off time by
eliminating inherent R-C delay times in measurements
Note 3
S1 e Open for timing test for push pull outputs
S1 e VCC for VOL test
S1 e GND for VOH test
S1 e VCC for High Impedance to active low and
active low to High Impedance measurements
e
GND for High Impedance to active high and
active high to High Impedance measurements
Note 4
Pull-up load for CHRDY e 1kX
IO16 e 300X
M16 e 300X
Pin Capacitance TA e 25 C f e 1 MHz
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
7
pF
COUT
Output Capacitance
10
pF
DERATING FACTOR
Output timing is measured with a purely capacitive load of
50 pF or 240 pF The following correction factor can be
used for other loads (Note This factor is preliminary)
Derating for 3SL MOS e E005 nspF
Derating for 3SH OCL TPI e E003 nspF
AUI Transmit Test Load
TLF11498 – 62
Note
In the above diagram the TXa and TXb signals are taken from the
AUI side of the isolation (pulse transformer) The pulse transformer used for
all testing is a 100 mH g01% Pulse Engineering PE64103
79



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