DP83905AVQB datasheet(75/80 Pages) NSC

75 / 80 page

80 Preliminary Switching Characteristics (Continued)

RESET Timing

TLF11498 – 55

Symbol

Description

Min

Max

Units

RESET Asserted Until IO Inactive Asserted (Note 1)

400

RESET Asserted Until RegLoad State Entered (Note 2)

415

RESET Deasserted Until RegLoad Deasserted (Note 3)

100

RESET Deasserted Until EELOAD State Entered (Note 4)

EELoad Width (Note 4)

320

Note 1

IO inactive is not an external signal It is used here to indicate the length of time RESET must be active before the ATLANTIC Controller recognizes it

begins to drive the ISA outputs to their inactive state and ignores ISA inputs except RESET

Note 2

RegLoad is not an external signal It is used here to indicate the length of time RESET must be active before the ATLANTIC Controller begins contiguring

When IOinactive goes active the internal pull-down resistors on the memory support buses are enabled

Note 3

If RegLoad is high the values on the memory support buses are Iatched into the configuration registers when RESET is deasserted The pull-down resistors

on this bus are enabled until RegLoad is deasserted

Note 4

EELoad is not an extemal signal it is used here to indicate when the EEPROM store is loading

Serial EEPROM Timing

TLF11498 – 56

Symbol

Description

Min

Max

Units

EECS Setup to SK

150

EECS Hold after SK

250

MSD2 Low Time

450

MSD2 High Time

450

MSD2 Clock Period (Note 1)

Data In Setup to MSD2 High

100

Data In Hold from MSD2 High

100

Data Out Valid from MSD2 High

500

Note 1

Derived from Crystal Oscillator Tolerance e g001%

DP83905AVQB Datasheet(PDF) 75 Page - National Semiconductor (TI)

DP83905AVQB Datasheet(HTML) 75 Page - National Semiconductor (TI)

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