DP83905AVQB datasheet(16/80 Pages) NSC

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40 Functional Description (Continued)

at the desired base IO address If desired the configuration

software could change the EEPROM content to the new

values eliminating the need to reconfigure upon each power

up Alternately the software could leave the EEPROM alone

and execute the configuration using the printer port’s data

only work once after each power-up Therefore the user

cannot enable the ATLANTIC Controller from reserved

mode change it back into reserved mode and enable it

again A power-on reset must occur between the first time it

is enabled from the reserved mode and the second

A second consideration is the location of the boot PROM in

the system memory map which also has the same conflict

and programming considerations as the IO address selec-

tion However the solution is different primarily because the

boot PROM must be configured before power up This is

because during normal usage of the boot PROM the PC’s

BIOS will look for the ROM immediately after reset not al-

lowing configuration software to first select the boot PROM

addressing prior to usage

To configure the boot PROM without jumpers the configura-

tion software must first power up the ATLANTIC Controller

configure the EEPROM to the desired location then hard-

ware reset the ATLANTIC Controller After the reset the

ATLANTIC Controller’s EEPROM will load in the desired

boot PROM configuration automatically during the reset

Now after reset when the PC scans for the boot PROM the

ROM will be correctly mapped in the memory space en-

abling the network boot operation to proceed

Ethernet Cable Configuration

ATLANTIC Controller offers the choice of all the possible

Ethernet cabling options that is Ethernet (10BASE5) Thin

Ethernet (10BASE2) and Twisted-pair Ethernet (10BASE-T)

The type of cabling used is controlled by Configuration Reg-

ister B ATLANTIC Controller also supplies a THIN output

signal which can be used to disableenable an external

DC – DC converter which is required for 10BASE2

45 LOW POWER OPERATION

The ATLANTIC Controller has a low power support mode

that can be used to disable the Ethernet port and conserve

power It should be noted that the device is not operational

in this mode and requires to be initialized after exiting this

mode

The power and ground pins to the ATLANTIC Controller

are split up into two groups interface and core By switching

the power off to the core logic while still powering the inter-

face logic the ATLANTIC Controller can be powered down

without crashing the ISA bus The LOWPWR pin should be

driven high to indicate that the device is about to go into low

power then the power to the VDD pins should be switched

off The same signal that is used to drive the LOWPWR pin

can be used to drive a p-channel load switch to disable

power to the core This switch must have a very low on

resistance to minimize the voltage difference between the

VCC and the lFVCC All devices on the memory support bus

should also be powered from the VCC supply

46 BOOT PROM OPERATION

The ATLANTIC Controller supports an optional boot

PROM the address and size of which can be set in Configu-

ration Register C This boot PROM can be any 8 bits wide

storage device implemented with a non-volatile technology

Write cycles to this device can be enabled and disabled by

programming Configuration Register B This can be used to

prevent unwanted write cycles to certain devices such as a

Flash EEPROM It should be noted that the address pins

for the boot PROM should be connected directly to the

ISA bus

The ATLANTIC Controller supplies the chip se-

lect to the device and buffers the data onto and from the

ISA bus so the memory support data bus should be con-

nected to the boot PROM’s data pins

47 DP8390 CORE (NETWORK INTERFACE

CONTROLLER)

The DP8390 Core logic

Figure 12 contains the Serializer

Deserializer which is controlled by the Protocol PLA DMA

Control FIFO Address Comparator Multicast Hashing Reg-

ister The DP8390 core implements all of the IEEE 8023

Media access control functions for the ATLANTIC Control-

ler and interfaces to the internal ENDEC (on the left of the

block diagram) and also interfaces to the Bus Interface and

memory support bus via a number of address data and con-

trol signal (and the right side of the block diagram) The

following sections describe the functions of the DP8390

core

Receive Deserializer

The Receive Deserializer is activated when the input signal

Carrier Sense is asserted to allow incoming bits to be shift-

ed into the shift register by the receive clock The serial

receive data is also routed to the CRC generatorchecker

The Receive Deserializer includes a synch detector which

detects the SFD (Start of Frame Delimiter) to establish

where byte boundaries within the serial bit stream are locat-

ed After every eight receive clocks the byte wide data is

transferred to the 16-byte FlFO and the Receive Byte Count

is incremented

The first six bytes after the SFD are

checked for valid comparison by the Address Recognition

Logic If the Address Recognition Logic does not recognize

the packet the FlFO is cleared

CRC GeneratorChecker

During transmission the CRC logic generates a local CRC

field for the transmitted bit sequence The CRC encodes all

fields after the synch byte The CRC is shifted out MSB first

following the last transmit byte During reception the CRC

logic generates a CRC field from the incoming packet This

local CRC is serially compared to the incoming CRC ap-

pended to the end of the packet by the transmitting node If

the local and received CRC match a specific pattern will be

generated and decoded to indicate no data errors Trans-

mission errors result in different patterns and are detected

resulting in rejection of a packet

DP83905AVQB Datasheet(PDF) 16 Page - National Semiconductor (TI)

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