ADF4107 datasheet(9/20 Pages) AD

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ADF4107

Rev. 0 | Page 9 of 20

FUNCTIONAL DESCRIPTION

Reference Input Stage

The Reference Input stage is shown in Figure 17. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

100k

Ω

REFIN

SW1

SW2

BUFFER

SW3

TO R COUNTER

POWER-DOWN

CONTROL

Figure 17. Reference Input Stage

RF Input Stage

The RF input stage is shown in Figure 18. It is followed by a

2-stage limiting amplifier to generate the CML clock levels

needed for the prescaler.

500

Ω

1.6V

500

Ω

AGND

BIAS

GENERATOR

RFINA

RFINB

AVDD

Figure 18. RF Input Stage

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B

counters, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF input stage and divides it

down to a manageable frequency for the CMOS A and B

counters. The prescaler is programmable. It can be set in

software to 8/9, 16/17, 32/33, or 64/65. It is based on a

synchronous 4/5 core. A minimum divide ratio is possible for

fully contiguous output frequencies. This minimum is

determined by P, the prescaler value, and is given by: (P2 – P).

A and B Counters

The A and B CMOS counters combine with the dual-modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are specified to work when the

prescaler output is 300 MHz or less. Thus, with an RF input

frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a

value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

equation for the VCO frequency is as follows:

()

[]

REFIN

VCO

fVCO

Output frequency of external voltage controlled

oscillator (VCO).

Preset modulus of dual-modulus prescaler

(8/9, 16/17, etc.).

Preset divide ratio of binary 13-bit counter

(3 to 8191).

Preset divide ratio of binary 6-bit swallow counter

(0 to 63).

fREFIN

External reference frequency oscillator.

LOAD

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

13-BIT B

COUNTER

TO PFD

6-BIT A

COUNTER

N DIVIDER

MODULUS

CONTROL

N = BP + A

Figure 19. A and B Counters

R Counter

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

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