PWM

8

7

6

5

4

9

P

GND

1

V

IN

SKIP#

V

SW

V

DD

P

GND

BOOT

BOOT_R

2

3

CSD97374Q4M

SLPS382C – JANUARY 2013 – REVISED JULY 2013

www.ti.com

PIN CONFIGURATION

Figure 13. Top View

PIN DESCRIPTION

PIN

DESCRIPTION

NO.

NAME

1

SKIP#

This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the

Sync FET. When SKIP# is High, the CSD97374Q4M operates in Forced Continuous Conduction Mode. A tri-state

voltage on SKIP# puts the driver into a very low power state.

2

Supply Voltage to Gate Drivers and internal circuitry.

3

Power Ground, Needs to be connected to Pin 9 and PCB

4

Voltage Switching Node – pin connection to the output inductor.

5

Input Voltage Pin. Connect input capacitors close to this pin.

6

BOOT_R

Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The

bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.

7

BOOT

8

PWM

Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate

high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if

9

Power Ground

6

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