FX021 datasheet(7/20 Pages) TI1

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UDG-12218

VUVLO_H

VUVLO_L

VVDD

Driver On

CSD97374Q4M

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SLPS382C – JANUARY 2013 – REVISED JULY 2013

Figure 14. Functional Block Diagram

FUNCTIONAL DESCRIPTION

POWERING CSD97374Q4M AND GATE DRIVERS

An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive

power for the MOSFETS. A 1µF 10V X5R or higher ceramic capacitor is recommended to bypass VDD pin to

PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply

to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and

BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of the Control FET and

reduce voltage spikes on the VSW node. A typical 1Ω to 4.7Ω value is a compromise between switching loss and

VSW spike amplitude.

Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control

FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H).,

Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower

UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the

Control FET and Sync FET gates actively low. Figure 15 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP# = Tri-state).

Figure 15. UVLO Operation

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