CSD97374Q4M

SLPS382C – JANUARY 2013 – REVISED JULY 2013

www.ti.com

RECOMMENDED PCB DESIGN OVERVIEW

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below

is a brief description on how to address each parameter.

Electrical Performance

The CSD97374Q4M has the ability to switch at voltage rates greater than 10kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

•

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

The example in Figure 19 uses 1 x 1nF 0402 25V and 3 x 10µF 1206 25V ceramic capacitors (TDK Part #

C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an

appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power

Stage C5, C8 and C6, C19 should follow in order.

•

BOOT_R pins

•

The switching node of the output inductor should be placed relatively close to the Power Stage

Thermal Performance

The CSD97374Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

•

Use the smallest drill size allowed in your design. The example in Figure 19 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

Figure 19. Recommended PCB Layout (Top Down View)

(2)

Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

12

Submit Documentation Feedback

Copyright © 2013, Texas Instruments Incorporated

Not Recommended For New Designs