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WM8962B Datasheet(PDF) 200 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 200 Page - Wolfson Microelectronics plc |
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200 / 295 page  WM8962 200 Rev 4.3 REGISTER MAP The WM8962 control registers are listed below. Note that only the register addresses described here should be accessed; writing to other addresses may result in undefined behaviour. Register bits that are not documented should not be changed from the default values. REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R0 (0h) Left Input volume 0 0 0 0 0 0 0 IN_VU INPGA L_MUT E INL_ZC INL_VOL [5:0] 009Fh R1 (1h) Right Input volume CUST_ID [3:0] CHIP_REV [2:0] IN_VU INPGA R_MUT E INR_Z C INR_VOL [5:0] 069Fh R2 (2h) HPOUTL volume 0 0 0 0 0 0 0 HPOUT _VU HPOUT L_ZC HPOUTL_VOL [6:0] 0000h R3 (3h) HPOUTR volume 0 0 0 0 0 0 0 HPOUT _VU HPOUT R_ZC HPOUTR_VOL [6:0] 0000h R4 (4h) Clocking1 0 0 0 0 0 DSPCLK_DIV [1:0] (K) ADCSYS_CLK_DIV [2:0] (K) DACSYS_CLK_DIV [2:0] (K) SYSCLK_DIV [1:0] (K) 0 0020h R5 (5h) ADC & DAC Control 1 0 0 0 0 0 0 0 0 0 ADCR_ DAT_I NV ADCL_ DAT_I NV DAC_M UTE_R AMP DAC_M UTE DAC_DEEMP [1:0] ADC_H PF_DIS 0018h R6 (6h) ADC & DAC Control 2 0 0 ADC_HPF_SR [1:0] (K) 0 ADC_H PF_MO DE ADC_HPF_CUT [2:0] DACR_ DAT_I NV DACL_ DAT_I NV 0 DAC_U NMUT E_RAM P DAC_M UTERA TE 0 DAC_H P 2008h R7 (7h) Audio Interface 0 0 0 0 AIFDA C_TDM _MOD E AIFDA C_TDM _SLOT AIFAD C_TDM _MOD E AIFAD C_TDM _SLOT ADC_L RSWA P BCLK_I NV MSTR DAC_L RSWA P LRCLK _INV WL [1:0] FMT [1:0] 000Ah R8 (8h) Clocking2 0 0 0 0 CLKRE G_OVD MCLK_SRC [1:0] CLASSD_CLK_DIV [2:0] (K) SYSCL K_ENA 0 BCLK_DIV [3:0] 01E4h R9 (9h) Audio Interface 1 0 0 0 0 AUTO MUTE_ STS 0 DAC_AUTOMU TE_SAMPLES [1:0] DAC_A UTOM UTE 0 0 DAC_C OMP DAC_C OMPM ODE ADC_C OMP ADC_C OMPM ODE LOOPB ACK 0300h R10 (Ah) Left DAC volume 0 0 0 0 0 0 0 DAC_V U DACL_VOL [7:0] 00C0h R11 (Bh) Right DAC volume 0 0 0 0 0 0 0 DAC_V U DACR_VOL [7:0] 00C0h R14 (Eh) Audio Interface 2 0 0 0 0 0 AIF_RATE [10:0] 0040h R15 (Fh) Software Reset SW_RESET [15:0] 0000h R17 (11h) ALC1 0 0 0 0 0 ALC_IN ACTIV E_ENA ALC_L VL_MO DE ALCL_ ENA ALCR_ ENA ALC_MAXGAIN [2:0] ALC_LVL [3:0] 007Bh R18 (12h) ALC2 ALC_L OCK_S TS ALC_T HRESH _STS ALC_S AT_ST S ALC_P KOVR_ STS ALC_N GATE_ STS 0 0 0 ALC_Z C ALC_MINGAIN [2:0] ALC_HLD [3:0] 0000h R19 (13h) ALC3 0 0 0 ALC_NGATE_GAIN [2:0] 0 ALC_M ODE ALC_DCY [3:0] ALC_ATK [3:0] 1C32h R20 (14h) Noise Gate ALC_NGATE_DCY [3:0] ALC_NGATE_ATK [3:0] ALC_NGATE_THR [4:0] ALC_NGATE_M ODE [1:0] ALC_N GATE_ ENA 3200h R21 (15h) Left ADC volume 0 0 0 0 0 0 0 ADC_V U ADCL_VOL [7:0] 00C0h R22 (16h) Right ADC volume 0 0 0 0 0 0 0 ADC_V U ADCR_VOL [7:0] 00C0h R23 (17h) Additional control(1) 0 0 0 0 0 0 0 THERR _ACT 0 0 ADC_H P 0 0 0 0 TOCLK _ENA 0100h |
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