PC87393 datasheet(108/148 Pages) NSC

108 / 148 page

7.0 X-Bus Extension (Continued)

108

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Figure 23. LPC to X-Bus Address Translation: Legacy and Extended Legacy BIOS Ranges

7.3.3

Extended Read/Write Signal Mode

This mode is essential for devices that have separate read and write signals for memory transactions and for I/O transac-

tions. While in this mode, the PC8739x routes I/O read and write signals to XIORD and XIOWR pins, and memory or FWH

read and write signals to XRD and XWR.

If the PC8739x is set to wake-up with the X-Bus signals configured to output pins (using strap pins XCNF2-0), the extended

mode is disabled, and must be re-enabled by the user.

7.3.4

Indirect Memory Read and Write Transaction

I/O mapped registers may be used through an LPC I/O transaction to perform an X-Bus memory transaction. This mecha-

nism uses the following X-Bus module registers:

Four Indirect Memory Address registers, XIMA3-XIMA0, representing address bits 31 to 0

One Indirect Memory Data register (XIMD), representing data bits 7 to 0

Two enable bits, one for each Select Conﬁguration register, XZCNF0[5] and XZCNF1[5].

Following a write to the XIMD register, a memory write cycle appears on the X-Bus using the addresses and data from the

XIMA3-XIMA0 and XIMD registers. Following a read from the XIMD register, a memory read cycle appears on the X-Bus

using the addresses from these same registers. The returned data from the X-Bus cycle is used to finish the LPC I/O read

cycle from XIMD register.

The read or write cycles appear only if one of the Indirect Memory Cycle Enable bits (XZCNF0[5] or XZCNF1[5]) is set. If

both of these bits are set, select 1 is ignored and the transaction takes place according to select 0 settings. All X-Bus cycle

configurations are the same as defined in the X-Bus Select Configuration registers (XZCNF0 and XZCNF1).

7.3.5

Normal Address Mode X-Bus Transactions

The read and write transactions in Normal address mode are similar to those used in the X-Bus or ISA bus. At least two idle

cycles are inserted at the end of each X-Bus transaction cycle (there may be more idle cycles due to the LPC transactions).

Once a read cycle on the LPC falls within the range of any of the enabled decoded address ranges of the X-Bus functional

block, a read cycle begins. A read cycle (Figure 24) starts by outputting the address signals on address signals XA19-0 on

the rising edge of the clock. During this time, the PC8739x does not drive the data bus signals XD7-0. One LPC clock cycle

later, a chip select signal XCS1 or 0 is asserted, based on the address accessed and the select signal mapping. Three clock

cycles later, on the next rising edge of the clock, the XRD signal is asserted (set to 0) indicating that this is a read cycle and

enabling the device being accessed to drive the data bus within 16 clock cycles plus the internally programmed wait state

period. If XRDY use is enabled for this zone, XRDY input value is then checked on the rising edge of the clock, and the trans-

action is extended until XRDY is detected to be high. Four clock cycles later, the input data XD7-0 is sampled on the rising

edge of the clock. One LPC clock cycle later, XRD is de-asserted (set to 1) and one clock cycle later, the transaction is com-

pleted by de-asserting XCS1-0. The address is retained for the duration of two more cycles, after which the address lines

change their values to 0.

LPC Bus Address

FFFFFFFFh

xFFFFFFFh

X-Bus Address

000FFFFFh

xFFE0000h

00000000h

000F0000h

000EFFFFh

000E0000h

Legacy BIOS

Extended

Legacy BIOS

PC87393 Datasheet(PDF) 108 Page - National Semiconductor (TI)

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