PC87393 datasheet(110/148 Pages) NSC

110 / 148 page

7.0 X-Bus Extension (Continued)

110

www.national.com

Figure 25. Write Access Cycle - Normal Address Mode

7.3.6

Latched Address Mode X-Bus Transactions

The read and write transactions in Latched address mode are similar to those used in Normal address mode, except for how

the addresses are placed on the X-Bus. In this mode, address signals 27-0 are output using the XA signals and via multi-

plexing over the data bus (XD7-0). Latch control signals XSTB2-0 help a system capture these signals. The XSTB2-0 signals

are placed as long as the address signal are valid (until the end of a transaction).

Once a read cycle on the LPC falls within the range of any of the enabled X-Bus decoded address ranges, a read cycle

begins. A read cycle starts by outputting the lower twenty address signals on address signals XA19-0, and address signals

27-20 on data signals XD7-0, on the rising edge of the clock. Two clock cycles later, a strobe signal (XSTB2) is asserted to

latch the information on an external latch. Two clock cycles later, a second set of address signals, 19-12, is placed on data

pins XD7-0. These may be latched using the strobe signal XSTRB1 output two cycles later on the rising edge of the clock.

Two clock cycles later, the last group of address signals, 11-4, is output on data signals XD7-0. The XSTRB0 output two

cycles later, on the rising edge of the clock, may be used to latch this part of the address. Two cycles later on the rising edge

of the clock, the PC8739x stops driving the data bus. At this point, all addresses are available either on the address outputs

of the PC8739x (XA19-0) or in one of the three latches. The system may require only part of these addresses, depending

on the size of the address memory or peripheral space. One clock cycle later, a chip select signal XCS1 or 0 is asserted,

based on the address accessed and the select signal mapping. From this point, the read continues as described for the Nor-

mal address mode. XSTRB2-0 are deasserted when the address becomes invalid.

Once a write cycle on the LPC falls within the range of any of the enabled decoded address ranges of the X-Bus functional

block, a read cycle is started. A write cycle starts by outputting the lower twenty address signals on address signals XA19-

0] and address signals 27- 20 on data signals XD7-0, on the rising edge of the clock. Two clock cycles later, a strobe signal

(XSTB2) is asserted to latch the information on an external latch. Two clock cycles later, a second set of address signals,

19-12, is placed on data pins XD7-0. These may be latched using the strobe signal XSTRB1 output two cycles later on the

rising edge of the clock. Two clock cycles later, the last group of address signals, 11-4, is output on the data signals XD7-0.

The XSTRB0 output, two cycles later on the rising edge of the clock, may be used to latch this part of the address. Two

cycles later on the rising edge of the clock, the PC8739x outputs the data signals on data pins XD7-0 on the rising edge of

the clock. At this point, all the address is available either on the address outputs of the PC8739x (XA[19:0]) or in one of the

three latches. The system may require only part of these addresses, depending on the size of the address memory or pe-

ripheral space. One clock cycle later, chip select signal XCS1 or 0 is asserted, based on the address accessed and the select

signal mapping. From this point, the write continues as described for the Normal address mode. XSTRB2-0 are deasserted

when the address becomes invalid.

CLK

(Internal for Reference)

XD7-0

XA19-0

XCS1-0

XWR

Insert 12+”Programmed Wait States” of 33 MHz clocks here.

All non-clock signals remain the same during this inserted time.

XRD

XRDY

PC87393 Datasheet(PDF) 110 Page - National Semiconductor (TI)

PC87393 Datasheet(HTML) 110 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL