PC87393 datasheet(116/148 Pages) NSC

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7.0 X-Bus Extension (Continued)

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7.4.5

X-Bus PIRQx Input Registers (XIRQCA to XIRQCD)

This set of four registers defines the mapping of the four PIRQ signals. Each registers is associated with one of the four

PIRQ inputs, as follows:

Location:

Offset 04h (XIRQCA)

Location:

Offset 05h (XIRQCB)

Location:

Offset 06h (XIRQCC)

Location:

Offset 07h (XIRQCD)

Type:

R/W

Table 32. IRQ Polarity Control

Bit

76543210

Name

Reserved

PIRQ

Polarity

Inversion

PIRQ

Enable

PIRQ

Polarity

PWUREQ

Enable

Reset

00000000

Bit

Description

7-4

Reserved

PIRQ Polarity Inversion. This bit controls the polarity of the IRQ signal sent through the IRQ Serializer (see

Table 32). This bit is reset to ’0’.

PIRQ Enable. When this bit is set, it enables the interrupt. Ignored when the IRQ is mapped to zero (see

Section 2.2.3).

Disabled (default).

Enabled.

PIRQ Polarity. This bit speciﬁes the active level of the incoming IRQ signal.

Active low (default).

1: Active high.

Power-Up Request Enable. An IRQ event is routed to the PWUREQ output.

0: Disabled (default).

1: Enabled.

PIRQ Polarity

Inversion

PIRQ Polarity

Serial IRQ Polarity

PIRQx

PC87393 Datasheet(PDF) 116 Page - National Semiconductor (TI)

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