LM3530 datasheet(27/50 Pages) TI1

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Bit 7

Bit 6

Bit 5

Bit 4

R/W

Bit 0

Bit 1

I2C Compatible Address

MSB

Bit 3

Bit 2

LSB

Bit 7

Bit 6

Bit 5

Bit 4

R/W

Bit 0

Bit 1

I2C Compatible Address

MSB

LSB

Bit 3

Bit 2

Start Condition

Stop Condition

SDA

SCL

LM3530

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SNVS606L – JUNE 2009 – REVISED DECEMBER 2014

8.5 Programming

8.5.1 I2C-Compatible Interface

8.5.1.1 Start and Stop Condition

The LM3530 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning

and the end of the I2C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL

is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C

master always generates the START and STOP conditions. The I2C bus is considered busy after a START

condition and free after a STOP condition. During data transmission, the I2C master can generate repeated

START conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA

must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be

changed when SCL is LOW.

Figure 38. Start and Stop Sequences

8.5.1.2 I2C-Compatible Address

The 7bit chip address for the LM3530 is (0x38, or 0x39) for the 40-V version and (0x36) for the 25-V version.

After the START condition, the IC master sends the 7-bit chip address followed by an eighth bit (LSB) read or

write (R/W). R/W= 0 indicates a WRITE and R/W = 1 indicates a READ2. The second byte following the chip

address selects the register address to which the data will be written. The third byte contains the data for the

selected register.

Figure 39. I2C-Compatible Chip Address (0x38)

Figure 40. I2C-Compatible Chip Address (0x36)

8.5.1.3 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte

of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is

generated by the master. The master then releases SDA (HIGH) during the 9th clock pulse. The LM3530 pulls

down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte

has been received.

There are fourteen 8-bit registers within the LM3530 as detailed in Table 4.

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