DP8432V datasheet(25/56 Pages) NSC

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50 Refresh Options (Continued)

53 EXTENDING REFRESH

The programmed number of periods of CLK that refresh

RASs are asserted can be extended by one or multiple peri-

ods of CLK Only the all RAS (with or without error scrub-

bing) type of refresh can be extended To extend a refresh

cycle the input extend refresh EXTNDRF must be assert-

ed before the positive edge of CLK that would have negated

all the RAS outputs during the refresh cycle and after the

positive edge of CLK which starts all RAS outputs during the

refresh as shown in

Figure 19 This will extend the refresh to

the next positive edge of CLK and EXTNDRF will be sam-

pled again The refresh cycle will continue until EXTNDRF is

sampled low on a positive edge of CLK

TLF11118 – 28

FIGURE 19 Extending Refresh with the Extend Refresh (EXTNDRF) Input

60 Port A Wait State Support

Wait states allow a CPU’s access cycle to be increased by

one or multiple CPU clock periods The wait or ready input is

named differently by CPU manufacturers However any

CPU’s wait or ready input is compatible with either the WAIT

or DTACK output of the DP8430V31V32V The user de-

termines whether to program WAIT or DTACK (R7) and

which value to select for WAIT or DTACK (R2 R3) depend-

ing upon the CPU used and where the CPU samples its wait

input during an access cycle

The decision to terminate the CPU access cycle is directly

affected by the speed of the DRAMs used The system de-

signer must ensure that the data from the DRAMs will be

present for the CPU to sample or that the data has been

written to the DRAM before allowing the CPU access cycle

to terminate

The insertion of wait states also allows a CPU’s access cy-

cle to be extended until the DRAM access has taken place

The DP8430V31V32V insert wait states into CPU access

cycles due to guaranteeing precharge time refresh current-

ly in progress user programmed wait states the WAITIN

signal being asserted and GRANTB not being valid

(DP8432V only) If one of these events is taking place and

the CPU starts an access the DP8430V31V32V will insert

wait states into the access cycle thereby increasing the

length of the CPU’s access Once the event has been com-

pleted the DP8430V31V32V will allow the access to take

place and stop inserting wait states

There are six programming bits R2 – R7 an input WAITIN

and an output that functions as WAIT or DTACK

61 WAIT TYPE OUTPUT

With the R7 address bit negated during programming the

user selects the WAIT output As long as WAIT is sampled

asserted by the CPU wait states (extra clock periods) are

inserted into the current access cycle as shown in

Figure

20 Once WAIT is sampled negated the access cycle is

completed by the CPU WAIT is asserted at the beginning of

a chip selected access and is programmed to negate a

number of positive edges andor negative levels of CLK

from the event that starts the access WAIT can also be

programmed to function in pageburst mode applications

Once WAIT is negated during an access and the ECAS

inputs are negated with AREQ asserted WAIT can be pro-

grammed to toggle following the ECAS inputs Once AREQ

is negated ending the access WAIT will stay negated until

the next chip selected access For more details about WAIT

Type Output see Application Note AN-773

TLF11118 – 29

FIGURE 20 WAIT Type Output

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