DP8432V datasheet(54/56 Pages) NSC

54 / 56 page

140 DP8430V31V32V User Hints

1 All inputs to the DP8430V31V32V should be tied high

low or the output of some other device

Note One signal is active high COLINC (EXTNDRF) should be tied low

to disable

2 Each ground on the DP8430V31V32V must be decou-

pled to the closest on-chip supply (VCC) with 01 mF ce-

ramic capacitor

This is necessary because these

grounds are kept separate inside the DP8430V31V32V

The decoupling capacitors should be placed as close as

possible with short leads to the ground and supply pins of

the DP8430V31V32V

3 The output called ‘‘CAP’’ should have a 01 mF capacitor

to ground

4 The DP8430V31V32V has 20X series damping resis-

tors built into the output drivers of RAS CAS address

and WE RFRQ Space should be provided for external

damping resistors on the printed circuit board (or wire-

wrap board) because they may be needed The value of

these damping resistors (if needed) will vary depending

upon the output the capacitance of the load and the

characteristics of the trace as well as the routing of the

trace The value of the damping resistor also may vary

between the wire-wrap board and the printed circuit

board To determine the value of the series damping re-

sistor it is recommended to use an oscilloscope and look

at the furthest DRAM from the DP8430V31V32V The

undershoot of RAS CAS WE and the addresses should

be kept to less than 05V below ground by varying the

value of the damping resistor The damping resistors

should be placed as close as possible with short leads to

the driver outputs of the DP8430V31V32V

5 The circuit board must have a good VCC and ground

plane connection If the board is wire-wrapped the VCC

and ground pins of the DP8430V31V32V the DRAM

associated logic and buffer circuitry must be soldered to

the VCC and ground planes

6 The traces from the DP8430V31V32V to the DRAM

should be as short as possible

7 Parameter Changes due to Loading

All AC parameters are specified with the equivalent load

capacitances including traces of 64 DRAMs organized

as 4 banks of 18 DRAMs each Maximums are based on

worst-case conditions If an output load changes then the

AC timing parameters associated with that particular

output must be changed For example if we changed our

output load to

C e 250 pF loads on RAS0 – 3 and CAS0–3

C e 760 pF loads on Q0 – 9 and WE

we would have to modify some parameters (not all calcu-

lated here)

$308a clock to CAS asserted

(tRAH e 15 ns tASC e 0 ns)

A ratio can be used to figure out the timing change per

change in capacitance for a particular parameter by using

the specifications and capacitances from heavy and light

load timing

Ratio e

$308a wHeavy Load b $308a wLight Load

CH(CAS) b CL(CAS)

79 ns b 72 ns

125 pF b 50 pF

7ns

75 pF

$308a (actual) e (capacitance difference c

ratio) a $308a (specified)

(250 pF b 125 pF)

7ns

75 pF

79 ns

117 ns a 79 ns

907 ns

250 pF load

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