DP8432V datasheet(34/56 Pages) NSC

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100 Dual Accessing (DP8432V)

The DP8432V has all the functions previously described In

addition to those features the DP8432V also has the capa-

bilities to arbitrate among refresh Port A and a second port

Port B This allows two CPUs to access a common DRAM

array DRAM refresh has the highest priority followed by the

currently granted port The ungranted port has the lowest

priority The last granted port will continue to stay granted

even after the access has terminated until an access re-

quest is received from the ungranted port (see

Figure 30a )

The dual access configuration assumes that both Port A

and Port B are synchronous to the system clock If they are

not synchronous to the system clock they should be exter-

nally synchronized (Ex By running the access requests

through several Flip-Flops see

Figure 32a )

101 PORT B ACCESS MODE

Port B accesses are initiated from a single input AREQB

When AREQB is asserted an access request is generated

If GRANTB is asserted and a refresh is not taking place or

precharge time is not required RAS will be asserted when

AREQB is asserted Once AREQB is asserted it must stay

asserted until the access is over AREQB negated negates

RAS as shown in

Figure 30b Note that if ECAS0 e 1 during

programming the CAS outputs may be held asserted (be-

yond RASn negating) by continuing to assert the appropri-

ate ECASn inputs (the same as Port A accesses) If Port B

is not granted the access will begin on the first or second

positive edge of CLK after GRANTB is asserted (See R0

R1 programming bit definitions) as shown in

Figure 30c as-

suming that Port A is not accessing the DRAM (CS ADS

ALE and AREQ) and RAS precharge for the particular bank

has completed It is important to note that for GRANTB to

transition to Port B Port A must not be requesting an ac-

cess at a rising clock edge (or locked) and Port B must be

requesting an access at that rising clock edge Port A can

request an access through CS and ADS ALE or CS and

AREQ Therefore during an interleaved access where CS

and ADS ALE become asserted before AREQ from the pre-

vious access is negated Port A will retain GRANTB e 0

whether AREQB is asserted or not

Since there is no chip select for Port B AREQB must incor-

porate this signal This mode of accessing is similar to Mode

1 accessing for Port A

TLF11118 – 45

Explanation of Terms

AREQA e

Chip Selected access request from Port A

AREQB e

Chip Selected access request from Port B

LOCK e

Externally controlled LOCKing of the Port

that is currently GRANTed

FIGURE 30a DP8432V Port APort B Arbitration

State Diagram This arbitration may take place

during the ‘‘ACCESS’’ or ‘‘REFRESH’’

state (see

Figure 13 )

TLF11118 – 46

FIGURE 30b Access Request for Port B

TLF11118 – 47

FIGURE 30c Delayed Port B Access

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