DP8432V datasheet(35/56 Pages) NSC

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100 Dual Accessing (DP8432V) (Continued)

102 PORT B WAIT STATE SUPPORT

Advanced transfer acknowledge for Port B ATACKB is

used for wait state support for Port B This output will be

asserted when RAS for the Port B access is asserted as

shown in

Figures 31a and 31b Once asserted this output

will stay asserted until AREQB is negated With external

logic ATACKB can be made to interface to any CPU’s wait

input as shown in

Figure 31c

103 COMMON PORT A AND PORT B DUAL PORT

FUNCTIONS

An input LOCK and an output GRANTB add additional

functionality to the dual port arbitration logic LOCK allows

Port A or Port B to lock out the other port from the DRAM

When a Port is locked out of the DRAM wait states will be

inserted into its access cycle until it is allowed to access

memory GRANTB is used to multiplex the input control sig-

nals and addresses to the DP8432V

1031 GRANTB Output

The output GRANTB determines which port has current ac-

cess to the DRAM array GRANTB asserted signifies Port B

has access GRANTB negated signifies Port A has access

to the DRAM array

TLF11118 – 48

FIGURE 31a Non-Delayed Port B Access

TLF11118 – 49

FIGURE 31b Delayed Port B Access

TLF11118 – 50

A Extend ATACK to

Clock) after RAS goes low

TLF11118 – 51

B Extend ATACK to 1T after RAS goes low

TLF11118 – 52

C Synchronize ATACKB to CPU B Clock This is useful if CPU B runs asynchronous to the DP8432

FIGURE 31c Modifying Wait Logic for Port B

DP8432V Datasheet(PDF) 35 Page - National Semiconductor (TI)