DP8432V datasheet(27/56 Pages) NSC

27 / 56 page

60 Port A Wait State Support (Continued)

TLF11118 – 32

FIGURE 22b WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’)

64 GUARANTEEING RAS LOW TIME

AND RAS PRECHARGE TIME

The DP8430V31V32V will guarantee RAS precharge time

between accesses between refreshes and between ac-

cess and refreshes The programming bits R0 and R1 are

used to program combinations of RAS precharge time and

RAS low time referenced by positive edges of CLK RAS

low time is programmed for refreshes only During an ac-

cess the system designer guarantees the time RAS is as-

serted through the DP8430V31V32V wait logic Since in-

serting wait states into an access increases the length of

the CPU signals which are used to create ADS or ALE and

AREQ the time that RAS is asserted can be guaranteed

The precharge time is also guaranteed by the DP8430V

31V32V Each RAS output has a separate positive edge

of CLK counter AREQ is negated setup to a positive edge

of CLK to terminate the access That positive edge is 1T

The next positive edge is 2T RAS will not be asserted until

the programmed number of positive edges of CLK have

passed as shown in

Figure 23 Once the programmed pre-

charge time has been met RAS will be asserted from the

positive edge of CLK However since there is a precharge

counter per RAS an access using another RAS will not be

delayed Precharge time before a refresh is always refer-

enced from the access RAS negating before RAS0 for the

refresh asserting After a refresh precharge time is refer-

enced from RAS3 negating for the refresh to the access

RAS asserting

TLF11118 – 33

FIGURE 23 Guaranteeing RAS Precharge (DTACK is Sampled at the ‘‘T2’’ Falling Clock Edge)

DP8432V Datasheet(PDF) 27 Page - National Semiconductor (TI)