DP8432V datasheet(42/56 Pages) NSC

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130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Difference

DP8430V31V32V-33

Number

Symbol

Parameter Description

Min

Max

Min

Max

tD1

(AREQ or AREQB Negated to RAS

Negated) Minus (CLK High to RAS

Asserted)

tD2

(CLK High to Refresh RAS Negated)

Minus (CLK High to RAS Asserted)

tD3a

(ADS Asserted to RAS Asserted

(Mode 1)) Minus (AREQ Negated

to RAS Negated)

tD3b

(CLK High to RAS Asserted (Mode 0))

Minus (AREQ Negated to RAS Negated)

tD4

(ECAS Asserted to CAS Asserted)

Minus (ECAS Negated to CAS Negated)

tD5

(CLK to Refresh RAS Asserted) Minus

(CLK to Refresh RAS Negated)

tD6

(AREQ Negated to RAS Negated)

Minus (ADS Asserted to RAS

Asserted (Mode 1))

DP8432V Datasheet(PDF) 42 Page - National Semiconductor (TI)

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