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TMS320DM641 Datasheet(PDF) 125 Page - Texas Instruments

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Part # TMS320DM641
Description  Video/Imaging Fixed-Point Digital Signal Processors
PDF  171 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM641 Datasheet(HTML) 125 Page - Texas Instruments

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Multichannel Audio Serial Port (McASP0) Peripheral
125
June 2003 − Revised August 2004
SPRS222C
Table 4−32. McASP0 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
3C00 0000 − 3C0F FFFF
RBUF/XBUFx
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT
registers, respectively].)
4.9.3
McASP0 Electrical Data/Timing
4.9.3.1
Multichannel Audio Serial Port (McASP) Timing
Table 4−33. Timing Requirements for McASP (see Figure 4−33 and Figure 4−34)
NO.
−400
−500
−600
UNIT
MIN
MAX
1
tc(AHCKRX)
Cycle time, AHCLKR/X
20
ns
2
tw(AHCKRX)
Pulse duration, AHCLKR/X high or low
10
ns
3
tc(CKRX)
Cycle time, ACLKR/X
ACLKR/X ext
33
ns
4
tw(CKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X ext
16.5
ns
5
tsu(FRXC-KRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
ACLKR/X int
5
ns
5
tsu(FRXC-KRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
ACLKR/X ext
5
ns
6
th(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
ACLKR/X int
5
ns
6
th(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
ACLKR/X ext
5
ns
7
tsu(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
ACLKR/X int
5
ns
7
tsu(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
ACLKR/X ext
5
ns
8
th(CKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X int
5
ns
8
th(CKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X ext
5
ns
Table 4−34. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 4−33 and Figure 4−34)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN
MAX
9
tc(AHCKRX)
Cycle time, AHCLKR/X
20
ns
10
tw(AHCKRX)
Pulse duration, AHCLKR/X high or low
10
ns
11
tc(CKRX)
Cycle time, ACLKR/X
ACLKR/X int
33
ns
12
tw(CKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X int
16.5
ns
13
td(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X int
−1
5
ns
13
td(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X ext
0
10
ns
14
td(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKX int
−1
5
ns
14
td(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKX ext
0
10
ns
15
tdis(CKRX−AXRHZ)
Disable time, AXR high impedance following last data bit from
ACLKR/X int
0
10
ns
15
tdis(CKRX−AXRHZ)
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
ACLKR/X ext
0
10
ns



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