TRF6901

SINGLECHIP RF TRANSCEIVER

SLWS110G − SEPTEMBER 2001 − REVISED JUNE 2004

12

POST OFFICE BOX 655303

detailed description (continued)

data slicer

The data slicer is a comparator circuit for received digital (FSK) data. The data slicer output voltage depends

on the difference between the received signal and a reference voltage (at the sample-and-hold (S&H) capacitor)

used as a decision threshold. During the learn mode, the S&H capacitor connected to terminal 34 is charged

up to the average dc voltage of a training sequence of alternating ones and zeroes; this establishes the

reference voltage to be used as a decision level before a sequence of actual data is received in the hold mode.

During long data transmissions, more training sequences may be necessary to recharge the S&H capacitor.

If the modulation scheme is dc-free (Manchester coding) or constant-dc, the TRF6901 may be operated

continuously in the learn mode, and no training sequence is necessary before the transmission of a data string.

However, the S&H capacitor voltage may be incorrect during power up or after long periods of inactivity (no data

transmission); a learning sequence before each data transmission is recommended.

The comparator is a CMOS circuit that does not load the S&H capacitor, so leaving the transmission gate

(learn/hold switch) open during periods of inactivity may be useful in maintaining the capacitor reference

voltage; however, it gradually discharges due to leakage current.

The time constant for charging the S&H capacitor is determined by its capacitance and an internal 50-k

Ω

resistor. A slow data rate requires a larger S&H capacitor (longer time constant). The value of the S&H capacitor,

Csh, can be calculated with the following equation:

Csh

^ 5

T

50000

where T is the bit period.

Low-Pass Amplifier

Csh{

Learn/Hold

50 k

Ω

34

LPF Out

Comparator

39

{External Sample-and-Hold Capacitor

33

Figure 6. Data Slicer

main divider

The main divider is composed of a 5-bit A-counter, a 9-bit B-counter, and a prescaler. The A-counter controls

the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33

until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count,

whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33

prescaler by:

where 0

Thus, the N-divider has a range of 992