TRF6901

SINGLECHIP RF TRANSCEIVER

SLWS110G − SEPTEMBER 2001 − REVISED JUNE 2004

23

POST OFFICE BOX 655303

C<6 :0>

DC−DC CLOCK DIVIDE FACTOR

1010110

172

1010111

174

1011000

176

1011001

178

1011010

180

1011011

182

1011100

184

1011101

186

1011110

188

1011111

190

1100000

192

1100001

194

1100010

196

1100011

198

1100100

200

1100101

202

1100110

204

1100111

206

1101000

208

1101001

210

1101010

212

1101011

214

1101100

216

1101101

218

1101110

220

1101111

222

1110000

224

1110001

226

1110010

228

1110011

230

1110100

232

1110101

234

1110110

236

1110111

238

1111000

240

1111001

242

1111010

244

1111011

246

1111100

248

1111101

250

1111110

252

1111111

254

NOTE:

C<6> is the MSB and C<0> is the LSB. The dc-dc clock divider is followed internally by a divide-by-2

stage to achieve a 50% duty cycle. This additional division is not included in the 7-bit setting. The

maximum valid divider factor is 254. The minimum valid divider factor is 2.