CLC5902 datasheet(20/28 Pages) NSC

20 / 28 page

Rev. 3.05 May 27, 1999

AGC

The CLC5902 AGC processor monitors the output level of

the ADC and servos it to the desired setpoint. The ADC

input is controlled by the DVGA to maintain the proper

setpoint level. DVGA operation results in a compression

of the signal through the ADC. The DVGA signal com-

pression is reversed in the CLC5902 to provide > 120dB

of linear dynamic range. This is illustrated in Figure 30.

In order to use the AGC the DRCS Control Panel software

should be used to calculate the programmable parameters.

To generate these parameters only the desired setpoint,

deadband+hysteresis, and loop time constant need to be

supplied. All subsequent calculations are performed by the

software. Complete details of the AGC operation are pro-

vided in an appendix but are not required reading.

AGC setpoint and deadband+hysteresis are illustrated in

Figure 31. The loop time constant is a measure of how fast

the loop will track a changing signal. Values down to

approximately 1.0 microsecond will be stable with the sec-

ond order LC noise filter. Since the DVGA operates with

6dB steps the deadband should always be greater than 6dB

to prevent oscillation. An increased deadband value will

reduce the amount of AGC operation. A decreased dead-

band value will increase the amount of AGC operation but

will hold the ADC output closer to the setpoint. The

threshold should be set so that transients do not cause sus-

tained overrange at the ADC inputs. The threshold setting

can also be used to set the ADC input near its optimal per-

formance level.

The AGC may be configured to free run, operate for a pro-

grammable period of time (burst mode), or stop running. If

a burst start pulse is applied to the AGC_EN pin in burst

mode, the AGC will free run for AGC_HOLD_COUNT

CK periods then freeze. At the beginning of the next burst

either the freeze value is maintained or an initial condition

is set from AGC_IC_A|B based on AGC_RESET_EN.

Allowing the AGC to free run should be appropriate for

most applications. Table 4 shows the AGC mode control

bits.

Power Management

The CLC5902 can be placed in a low power (static) state

by stopping the input clock. To prevent this from placing

the CLC5902 into unexpected states, the SI pin of the

CLC5902 should be asserted prior to disabling the input

clock and held asserted until the input clock has returned

to a stable condition.

Figure 30

Output Gain Scaling vs. Input Signal

Input Power

ADC Output

ADC Full Scale

AGC Threshold

Deadband+Hysteresis

Diversity Receiver

Chipset Full Scale

Figure 31

AGC Setup.

DVGA Input Power

Deadband

Hysteresis=Deadband-6dB

Reference

6dB

Setpoint

AGC Mode

AgcHldIC

AgcRstEn

AgcForce

Free Run

Burst, hold previous value

Burst, use initial conditions

Manual

100

Table 4

AGC Operating Modes

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