CLC5902 datasheet(15/28 Pages) NSC

15 / 28 page

Rev. 3.05 May 27, 1999

The CIC filter has a gain equal to N

4 (filter decimation^4)

which must be compensated for in the “SHIFT UP” circuit

shown in Figure 19 as well as Figure 15. This circuit has a

gain equal to 2(SCALE-44), where SCALE ranges from 0 to

40. This circuit divides the input signal by 244 providing

maximum headroom through the CIC filter. For optimal

noise performance the SCALE value is set to increase this

level until the CIC filter is just below the point of distor-

tion. A value is normally calculated and loaded for

SCALE such that

. The

actual gain of the CIC filter will only be unity for power-

of-two decimation values. In other cases the gain will be

somewhat less than unity.

Channel Gain

The gain of each channel can be boosted up to 42 dB by

shifting the output of the CIC filter up by 0 to 7 bits prior

to rounding it to 21 bits. For channel A, the gain of this

stage is:

, where GAIN_A ranges from 0

to 7. Overflow due to the GAIN circuit is saturated

(clipped) at plus or minus full scale. Each channel can be

given its own GAIN setting.

First Programmable FIR Filter (F1)

The CIC/GAIN outputs are followed by two stages of fil-

tering. The first stage is a 21 tap decimate-by-2 symmetric

FIR filter with programmable coefficients. Typically, this

filter compensates for a slight droop induced by the CIC

filter. In addition, it often provides stopband assistance to

F2 when deep stop bands are required. The filter coeffi-

cients are 16-bit 2’s complement numbers. Unity gain will

be achieved through the filter if the sum of the 21 coeffi-

cients is equal to 216. If the sum is not 216, then F1 will

introduce a gain equal to (sum of coefficients)/216. The 21

coe f fi ci ent s

a r e

ide n ti fi ed

c o ef fic i e n ts

where

is the center tap.

The coefficients are symmetric, so only the first 11 are

loaded into the chip.

Two example sets of coefficients are provided here. The

first set of coefficients, referred to as the standard set

(STD), compensates for the droop of the CIC filter provid-

ing a passband which is flat (0.01 dB ripple) over 95% of

the final output bandwidth with 70dB of out-of-band rejec-

tion (see Figure 20). The filter has a gain of 0.999 and is

symmetric with the following 11 unique taps (1|21, 2|20,

..., 10|12, 11):

29, -85, -308, -56, 1068, 1405, -2056, -6009,

1303, 21121, 32703

The second set of coefficients (GSM set) are intended for

applications that need deeper stop bands or need oversam-

pled outputs. These requirements are common in cellular

systems where out of band rejection requirements can

exceed 100dB (see Figure 21). They are useful for wide-

band radio architectures where the channelization is done

after the ADC. These filter coefficients introduce a gain of

0.984 and are:

-49, -340, -1008, -1617, -1269, 425, 3027, 6030,

9115, 11620, 12606

Second Programmable FIR Filter (F2)

The second stage decimate by two or four filter also uses

externally downloaded filter coefficients. The filter coeffi-

cients are 16-bit 2’s complement numbers. Unity gain will

be achieved through the filter if the sum of the 63 coeffi-

cients is equal to 216. If the sum is not 216, then the F2 will

introduce a gain equal to (sum of coefficients)/216.

The 63 coefficients are identified as

where

is the center tap. The coefficients are sym-

metric, so only the first 32 are loaded into the chip.

DATA

OUT

SCALE

Figure 19

Four-stage decimate by N CIC filter

Data @ FCK

= FS (FSAMPLE)

Data @ FCK/N

N = DEC + 1

22-bit input to SHIFT_UP is aligned

at the bottom of the 66-bit path when SCALE=0.

GAIN

SHIFTUP

GAIN

CIC

⋅

≤

GAIN

GAIN_A

1 n

() n

… 20

1 10

()

Figure 20

F1 STD frequency response

0.1

0.2

0.3

0.4

0.5

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

Frequency Response of F1 Using STD Set

Frequency Normalized To Filter Input Sample Rate

2 n

() n 0 … 62

2 31

()

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