Rev. 3.05 May 27, 1999

24

©1999 National Semiconductor Corporation

A block diagram of the AGC is shown in Figure 32. The

DVGA interface comprises four pins for each of the chan-

nels. The first three pins of this interface are a 3-bit binary

word that controls the DVGA gain in 6dB steps (AGAIN).

The final pin is ASTROBE which allows the AGAIN bits

to be latched into the DVGA’s register. A key feature of

the ASTROBE, illustrated Figure 33, is that it toggles

only if the data on AGAIN has changed from the previous

cycle. Not shown is that ASTROBE and BSTROBE are

independent. For example, ASTROBE should only toggle

when AGAIN has changed. BSTROBE should not toggle

because AGAIN has changed. This is done to minimize

unnecessary digital noise on the sensitive analog path

through the DVGA. ASTROBE and BSTROBE are

asserted during MR and SI to properly initialize the

DVGAs.

The absolute value circuit and the 2-stage, decimate-by-8

CIC filter comprise the power detection part of the AGC.

The power detector bandwidth is set by the CIC filter to

input frequency. This has the effect of reducing the power

For a full-scale sinusoidal input, the absolute value circuit

output is a dc value of

. Because the absolute

value circuit also generates undesired even harmonic

terms, the CIC filter (response shown in Figure 34), is

required to remove these harmonics. The first response

and the response magnitude is at least 25dB below the dc

from the absolute value circuit is about 10dB below the dc

this means that the ripple in the detected level is about

The “FIXED TO FLOAT CONVERTER” takes the fixed

point 9-bit output from the CIC filter and converts it to a

“floating point” number. This conversion is done so that

the 32 values in the RAM can be uniformly assigned (dB

AGC Theory of Operation

AGC_LOOP_GAIN

10

16

5

8

12

12

PERIOD

LOAD

EN

16

AGC_FORCE

AGC_HOLD_IC

-REF

LOG

FUNCTION PROGRAMMED

INTO RAM

AGC_EN

AGC_COUNT

AGC_IC_A

3

AIN[13:4]

9

AGC_RESET_EN

AGC_TABLE

AGAIN

Figure 32

CLC5902 AGC circuit, Channel A

EXP

ASTROBE

AGAIN[2:0]

CK

CK/8

1 SCK delay

ASTROBE does not pulse because AGAIN[2:0] does not change

Figure 33

Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 8 for detailed timing information.

511

2

π

⁄

()

⋅