CLC5902 datasheet(25/28 Pages) NSC

25 / 28 page

Rev. 3.05 May 27, 1999

scale) to detected power levels (54 db range). This pro-

vides a resolution of 1.7dB between detected power levels.

The truth table for this converter is given in Table 6. The

upper three bits of the output represent the exponent (e)

and the lower 2 are the mantissa (m). The exponent is

determined by the position of the leading ‘1’ out of the

CIC filter. An output of ‘001XX’ corresponds to a leading

‘1’ in bit 2 (LSB is bit 0). The exponent increases by one

each time the leading ‘1’ advances in bit position. The

mantissa bits are the two bits that follow the leading ‘1’. If

we define E as the decimal value of the exponent bits and

M as the decimal value of the mantissa bits, the output of

the CIC filter, POUT, corresponding to a given “FIXED TO

FLOAT CONVERTER” output is,

EQ. 5

The max() and min() operators account for row 1 of Table

6 which is a special case because M=POUT. Equation 5

associates each address of the RAM with a CIC filter out-

put.

As shown in Figure 32, the 32X8 RAM look-up table

implements the functions of log converter, reference sub-

traction, error amplifier, and deadband. The user must

build each of these functions by constructing a set of 8-bit,

2’s complement numbers to be loaded into the RAM. Each

of these functions and how to construct them are discussed

in the following paragraphs.

A log conversion is done in order to keep the loop gain

independent of operating point. To see why this is benefi-

cial, the control gain of the DVGA computed without log

conversion is,

EQ. 6

where G is the decimal equivalent of GAIN and Go

accounts for the DVGA gain in excess of unity. This equa-

tion assumes that the DVGA gain control polarity is posi-

tive as is the case for the CLC5526. The gain around the

entire loop must be negative. Observe in Equation 6 that

the control gain is dependent on operating point G. If we

instead compute the control gain with log conversion,

EQ. 7

which is no longer operating-point dependent. The log

function is constructed by computing the CIC filter output

associated with each address (Equation 5) and converting

these to dB. Full scale (dc signal) is

The reference subtraction is constructed by subtracting the

desired loop servo point (in dB) from the table values

computed in the previous paragraph. For example, if it is

desired that the DVGA servo the ADC input level (sinuso-

idal signal) to -6dBFS, the number to subtract from the

data is

EQ. 8

The table data will then cross through zero at the address

corresponding to this reference level. A deadband wider

than 6dB should then be constructed symmetrically about

this point. This prevents the loop from hunting due to the

6dB gain steps of the DVGA. Any deadband in excess of

6dB appears as hysteresis in the servo point of the loop as

illustrated in Figure 31. The deadband is constructed by

loading zeros into those addresses on either side of the one

which corresponds to the reference level.

The last function of the RAM table is that of error amplifi-

cation. All the operations preceding this one gave a table

slope

. This must now be adjusted in order to

control the time constant of the loop given by,

INPUT

OUTPUT

(eeemm)

0-3

000XX

4-7

001XX

8-15

010XX

16-31

011XX

32-63

100XX

64-127

101XX

128-255

110XX

256-511

111XX

Table 6

Fixed to Float Converter Truth Table

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-60

-50

-40

-30

-20

-10

Frequency Normalized to Sample Rate

Figure 34

Power detector filter response

OU T

4 min E 1

()

⋅

[]

max E 1

() 1

–

()

≥

⋅

DVGA

′

∂

–

()

⋅

(),

() 2

–

()

⋅

–

DVGA

∂

–

()

⋅

()

log

⋅

[],

6.02,

–

511

() 54dB

log

511

---------

---

⋅





44dB

log

RAM

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