Rev. 3.05 May 27, 1999

22

©1999 National Semiconductor Corporation

FREQ_A

4B

R/W

0

7-10

7:0

Frequency word for channel A. Format is a 32-bit, 2’s complement number spread across 4

PHASE_A

2B

R/W

0

11-12

7:0

Phase word for channel A. Format is a 16-bit, unsigned magnitude number spread across 2

registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_A/

2^16.

FREQ_B

4B

R/W

0

13-16

7:0

Frequency word for channel B. Format is a 32-bit, 2’s complement number spread across 4

PHASE_B

2B

R/W

0

17-18

7:0

Phase word for channel B. Format is a 16-bit, unsigned magnitude number spread across 2

registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_B/

2^16.

A_SOURCE

2

R/W

0

19

1:0

0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel

input source.

B_SOURCE

2

R/W

1

19

2:3

0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel

input source.

EXP_INH

1b

R/W

0

20

0

0=Allow exponent to pass into FLOAT TO FIXED converter. 1=Force exponent in DDC chan-

nel to a 7 (maximum digital gain). This affects both channels.

AGC_FORCE

1b

R/W

1

20

1

0=Enable AGC counter operation. 1=AGC loop operates continuously regardless of

AGC_EN pin. This affects both channels.

AGC_RESET_EN

1b

R/W

0

20

2

0=Initial condition is never used. 1=Integrator is reset each time the AGC transitions from

idle to active. This affects both channels.

AGC_HOLD_IC

1b

R/W

0

20

3

0=Normal closed-loop operation. 1=Hold integrator at initial condition. This affects both

channels.

AGC_LOOP_GAIN

2b

R/W

0

20

4:5

Bit shift value for AGC loop. Valid range is from 0 to 3. This affects both channels.

AGC_COUNT

2B

R/W

0

21-22

7:0

Counter value for AGC enable counter. Format is a 16-bit, unsigned magnitude number

spread across 2 registers. The LSBs are in the lower register. The value represents the num-

ber of CK cycles over which the loop is active.

AGC_IC_A

1B

R/W

0

23

7:0

AGC integrator initial condition for channel A. Format is an 8-bit, unsigned magnitude num-

ber. This number is written into the magnitude MSBs of the channel A AGC integrator when-

ever it is reset to the initial condition.

AGC_IC_B

1B

R/W

0

24

7:0

AGC integrator initial condition for channel B. Format is an 8-bit, unsigned magnitude num-

ber. This number is written into the magnitude MSBs of the channel B AGC integrator when-

ever it is reset to the initial condition.

AGC_RB_A

1B

R

0

25

7:0

AGC integrator readback value for channel A. Format is an 8-bit, unsigned magnitude num-

ber. The user can read the magnitude MSBs of the channel A integrator from this register.

AGC_RB_B

1B

R

0

26

7:0

AGC integrator readback value for channel B. Format is an 8-bit, unsigned magnitude num-

ber. The user can read the magnitude MSBs of the channel B integrator from this register.

TEST_REG

14b

R/W

0

27(LSBs)

28(MSBs)

7:0

5:0

Test input source. Instead of processing values from the AIN/BIN pins, the value from this

location is used instead. Format is 14-bit 2s complement number spread across 2 registers.

Reserved

1B

-

-

29

7:0

For future use.

Reserved

1B

-

-

30

7:0

For future use.

DEBUG_EN

1b

R/W

0

31

0

0=Normal. 1=Enables access to the internal probe points.

DEBUG_TAP

5b

R/W

0

31

1:5

Selects internal node tap for debug.

0 selects F1 output for BI, 20 bits

1 selects F1 output for BQ, 20 bits

2 selects F1 output for AQ, 20 bits

3 selects F1 output for AI, 20 bits

4 selects F1 input for BI, 20 bits

5 selects F1 input for BQ, 20 bits

6 selects F1 input for AI, 20 bits

7 selects F1 input for AQ, 20 bits

8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.

9 selects NCO A, sine output, 17 bits, 3 LSBs are 0.

10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0.

11 selects NCO B, sine output, 17 bits, 3 LSBs are 0.

12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0.

13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0.

14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0.

15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0.

16-31 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits from ch B, 2 LSBs are 0.

DITH_A

1b

R/W

1

31

6

0=Disable NCO dither source for channel A. 1=Enable.

DITH_B

1b

R/W

1

31

7

0=Disable NCO dither source for channel B. 1=Enable.

AGC_TABLE

32B

R/W

0

128-159

7:0

RAM space that defines key AGC loop parameters. Format is 32 separate 8-bit, 2’s comple-

ment numbers. This is common to both channels.

F1_COEFF

22B

R/W

0

160-181

7:0

Coefficients for F1. Format is 11 separate 16-bit, 2’s complement numbers, each one spread

across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in

address 160, h0[15:8] is in address 161, h1[7:0] is in address 162, h1[15:8] is in address

163.

F2_COEFF

64B

R/W

0

182-245

7:0

Coefficients for F2. Format is 32 separate 16-bit, 2’s complement numbers, each one spread

across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in

address 182, h0[15:8] is in address 183, h1[7:0] is in address 184, h1[15:8] is in address

185.

a. These are the default values set by a master reset (MR). Sync in (SI) will not affect any of these values.

Register Name

Width

Type

Addr

Bit

Description

Table 5

CLC5902 Control Registers