LP5551

SNVS417B – DECEMBER 2006 – REVISED APRIL 2013

www.ti.com

Pin Descriptions (continued)

Pin #

Name

I/O

Type

Description

13

NC

14

LDO3

P

P

LDO3 output, on-chip memory supply voltage

15

NC

16

FB1

P

P

AVS switcher feedback

17

PGND1

G

G

Power ground for the AVS switcher

18

PGND1

G

G

Power ground for the AVS switcher

19

PGND1

G

G

Power ground for the AVS switcher

20

SW1

P

P

AVS Switcher switch node; connected to inductor

21

PVDD1

P

P

Battery supply voltage for the AVS switcher

22

VDD_D

P

P

Battery supply voltage for digital

23

VDD_A

P

P

Battery supply voltage for analog

24

NC

25

PVDD2

P

P

Battery supply voltage for the DVS switcher

26

SW2

P

P

DVS Switcher switch node; connected to inductor

27

PGND2

G

G

Power ground for the DVS switcher

28

PGND2

G

G

Power ground for the DVS switcher

29

PGND2

G

G

Power ground for the DVS switcher

30

FB2

P

P

DVS switcher feedback

31

NC

32

SCAN

33

VPWELL

P

P

P-well bias voltage

34

NC

35

VNWELL

P

P

N-well bias voltage

36

NC

A: Analog Pin

D: Digital Pin

I: Input Pin

O: Output Pin

I/O: Input/Output Pin

P: Power Pin

G: Ground Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

Submit Documentation Feedback

Copyright © 2006–2013, Texas Instruments Incorporated

Product Folder Links: LP5551