LP5551

SNVS417B – DECEMBER 2006 – REVISED APRIL 2013

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N-Well Bias Characteristics

apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Accuracy

Output Voltage Offset Tolerance

Iout = 10 µA

-0.363

-0.3

-0.266

V

2.7

Line Regulation

0.321

%/V

2.7 V

Load Regulation

VAVS = 1.2 V

-0.107

%/mA

0.1 uA

≤ IOUT ≤ 10 uA

Programmable Output Voltage

Programming Resolution: See Register

-0.315

0

1

V

Range

Table

Quiescent Current

50

uA

Output Sourcing and Sinking

3

mA

Capability

Steady State

Output Source Short Circuit Limit

42

mA

Output Sink Short Circuit Limit

65

mA

Output Capacitance Of Load

0 µA

0.1

1

5

nF

(1)

All voltages are with respect to the potential at the GND pin.

(2)

All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested

during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and

temperature variations and applying statistical process control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

12

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