LP5551

www.ti.com

SNVS417B – DECEMBER 2006 – REVISED APRIL 2013

Absolute Maximum Ratings

(1) (2) (3)

VDD_A, VDD_D, PVDD1, and PVDD2

-0.3 to + 6.0V

LDO1, LDO2, LDO3, LDO4, VNWELL to GND, VPwell, ENABLE, RESETN, FB1, FB2, SW_AVS,

-0.3 to VDD_A + 0.3V

SW_DVS,GP0, GP1, GP2, and GP3

SPWI, SCLK, PWROK

-0.3 to VDD_D + 0.3V

GND, PGND1, PGND2, to GND SLUG

±0.3V

Junction Temperature (TJ-MAX)

150°C

Storage Temperature Range

-65°C to 150°C

TBD W

Maximum Lead Temperature (Soldering)

Human Body Model: All Pins

2.0kV

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4)

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-

OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance

of the part/package in the application (

(5)

For detailed soldering specifications and information, please refer to TI Application Note 1187: Leadless Leadframe Package (LLP)

(SNOA401).

(6)

The Human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin.The amount of Absolute Maximum

power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ –

TA)/

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.Internal thermal shutdown circuitry protects

the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C (typ.).

Operating Ratings

(1) (2)

VDD_A, VDD_D, PVDD1, and PVDD2

2.7 V to 5.5 V

−40°C to +125°C

(3)

−40°C to +85°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-

OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance

of the part/package in the application (

Thermal Properties

(4)

Junction-to-Ambient Thermal Resistance (

39.8°C/W

(4)

Junction-to-ambient thermal resistance (

θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set

forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of

thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm

(1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W.Junction-to-ambient thermal

resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care

must be paid to thermal dissipation issues in board design.The value of

material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT),

special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187:

Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.

Copyright © 2006–2013, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: LP5551