LP5551 datasheet(14/38 Pages) TI1

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LP5551

SNVS417B – DECEMBER 2006 – REVISED APRIL 2013

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Logic and Control Inputs

Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type

apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3) (4)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PWICLOCK

Rated frequency

2.7 V

≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V

MHz

VIL

ENABLE, RESETN, SPWI, SCLK

Input Low Level

0.4

2.7 V

≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V

VIH

ENABLE, RESETN

Input High Level

2.7 V

≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V

VIH_PWI

Input High Level, PWI

SPWI, SCLK, 1.5 V

≤VO2 ≤ 3.3 V

VO2-0.4V

IIL

ENABLE, RESETN,

Logic Input Current

-5

µA

0 V

≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V

IIL_PWI

Logic Input Current, PWI

SPWI, SCLK, 1.5 V

≤ VO2 ≤ 3.3 V

-5

µA

RPD_PWI

Pull-down resistance for PWI

0.5

Ω

signals

TEN_LOW

Minimum low pulse width to enter

ENABLE pulsed high - low - high

µsec

STARTUP state

(1)

All voltages are with respect to the potential at the GND pin.

(2)

All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested

during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and

temperature variations and applying statistical process control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

(4)

Specified by design.

Logic and Control Outputs

Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type

apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3) (4)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VOL

Output low level

PWROK, GPOx, SPWI, ISINK ≤ 1 mA

0.4

VOH

Output high level

PWROK, GPOx, ISOURCE ≤ 1 mA

VBAT1-0.4V

VOH_PWI

Output high level, PWI

SPWI, ISOURCE ≤ 1 mA

VO2-0.4V

(1)

All voltages are with respect to the potential at the GND pin.

(2)

All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested

during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and

temperature variations and applying statistical process control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

(4)

Specified by design.

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