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LP5551 Datasheet(PDF) 8 Page - Texas Instruments |
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LP5551 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 38 page ![]() LP5551 SNVS417B – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com LDO2 (I/O Voltage) Characteristics Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6 V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter Conditions Min Typ Max Units VOUT Accuracy IOUT = 125 mA, VOUT = 3.3 V, Output Voltage -3.7% 3.3 2.8% V 3.6 V ≤ VDD_A, _D ≤ 5.5 V VOUT Range Programmable Output Voltage 1.5-2.3 V = 100 mV step, 2.5 V, 2.8 V, 1.5 3.3 3.3 V Range 3.0 V and 3.3 V IOUT Rated Output Current 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V 0 250 mA Output Current Limit VOUT = 0V 615 Dropout Voltage(4) IOUT = 125 mA 65 192 mV IQ Quiescent Current IOUT = 0 mA (5) 55 µA ΔVOUT 3.6 V ≤ VDD_A, _D ≤ 5.5 V, Line Regulation -0.08 0.312 %/V IOUT = 125 mA VDD_A, _D, VPVDD1,2 = 3.6 V, Load Regulation -0.018 0.018 %/mA 1 mA ≤ IOUT ≤ 250 mA 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, Line Transient Regulation 24 mV TRISE,FALL = 10 us VDD_A, _D, VPVDD1,2 = 3.6 V, Load Transient Regulation 25 mA ≤ IOUT ≤ 225 mA, 246 mV TRISE,FALL = 100 ns eN Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz,COUT = 4.7 µF 0.120 mVRMS PSRR f = 1 kHz, COUT = 4.7 µF 46 dB Power Supply Ripple Rejection Ratio f = 10 kHz, COUT = 4.7 µF 34 COUT Output Capacitance 2 4.7 20 µF 0 mA ≤ IOUT ≤ 250 mA Output Capacitor ESR 5 500 m Ω tSTART-UP Start-Up Time from Shut-down COUT = 4.7 µF, IOUT = 250 mA 144 µs (1) All voltages are with respect to the potential at the GND pin. (2) All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (3) Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics (4) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.7V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V (5) Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference. 8 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP5551 |
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