UCD3028RMHT datasheet(31/81 Pages) TI1

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–1

–a11/K

–a21/K

b12

–a12

x(n)

b01/K

b11/K

y(n)

x(n–1)

y'(n–1)

x'(n–1)

y'(n–2)

y(n–1)

Clamp

InputScaler

and

Non-Linear Gain

From

EADC

Output

b21/K

x(n–2)

Coeff

Scaler

y'(n)

(=x'(n))

IIR

Control

Q15-to-Q0

Scaling

ypQ0(n)

yQ0(n)

Max

PRD

PRDor%of

PRD

yQ15(n)

UCD3040

UCD3028

UCD3020

www.ti.com

SLUS868H – DECEMBER 2009 – REVISED OCTOBER 2013

Figure 5. Compensator Architecture

The compensator also allows the minimum and maximum duty cycle to be programmed.

Compensator (CLA) Input

The input to the filter is a 6-bit signed number generated by the EADC. This number represents a 2s-complement

value of the power-supply output-voltage error signal (Vref – Vsense). This data value is registered on the

system clock inside the EADC, and a converted data-ready signal is supplied to start the filter operation on this

new data. The error inputs E(n – 1) and E(n – 2) are registered in the 6-bit format to save space. The current

E(n) is not registered inside the filter. The E(n) inputs to the filter can also come from a register that is

programmed by the user software. This happens only when the CPU sample-control bit is enabled. This allows

the CLA to be a math coprocessor for the UCD30xx CPU. The E(n), E(n – 1), and E(n – 2) values can only be

written by the user software by setting the filter-enable bit to 0.

Compensator Input Scaling

The input of the CLA is scaled to retain the physical meaning of the converted data and to implement nonlinear

control. The scaling function does two things. First, it divides the input by 1024, which approximately converts it

back to the millivolts (1/1000 V) scale that was converted. Second, it multiplies the input by a user-programmable

nonlinear gain, and the resulting 10-bit output of the scaler is applied to the filter input. During power-supply

control-loop design, the nominal gain value in the nonlinear gain table and the EADC analog front end (AFE) gain

must be taken into consideration. After the control design, if one of these values (nonlinear gain or AFE gain) is

changed, then the other one must be adjusted accordingly in order to maintain the same product (nonlinear gain

× AFE gain) and hence the same (designed) loop gain for the power supply. The following shows the AFE

control-bit settings, the corresponding AFE gain applied to the input, and the resulting EADC resolution.

Control bits = 0x3

→ 8× AFE gain → EADC resolution = 1mV/lsb

Control bits = 0x2

→ 4× AFE gain → EADC resolution = 2mV/lsb

Control bits = 0x1

→ 2× AFE gain → EADC resolution = 4mV/lsb

Control bits = 0x0

→ 1× AFE gain → EADC resolution = 8mV/lsb

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