UCD3028RMHT datasheet(39/81 Pages) TI1

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Event2 – Event1)

Cycle Adjust A

DPWM A

DPWM B

± Cycle Adjust

Negative Dead Time Supported

HR Edges

Event1

CLA Value

Event2

Event3

Event4

LR Edge

Dead Time1

ConstantDelta(Event3 – Event2)

Dead Time2

ConstantDelta(Period – Event4+Event1)

DPWM

Master

Start

DPWMSlave

Outputs

UCD3040

UCD3028

UCD3020

www.ti.com

SLUS868H – DECEMBER 2009 – REVISED OCTOBER 2013

Figure 9. Compensator Phase Mode (Phase-Shift Control) – DPWM Timing Diagram

Resonance Mode (Constant-On Duty Ratio With Variable Period)

•

DPWM B output is slaved and relative to DPWM A.

•

When the CLA is enabled for closed-loop operation, the event-2 comparison is controlled by the CLA duty-

output value.

–

The CLA value sets the pulse width of DPWM A.

•

When the CLA is enabled for closed-loop operation, the period is controlled by the CLA period-output value.

•

The initial settings of event 2 and event 3 (delta) are used for the calculation of the dead time between the

falling edge of DPWM A and the rising edge of DPWM B.

–

So, when the CLA is enabled for closed-loop operation, the calculated delta is used with the CLA duty-

output value to place event 3.

•

The initial settings of period and event 4 (delta) are used for the calculation of the dead time between the

falling edge of DPWM B and rising edge of DPWM A.

–

So, when the CLA is enabled for closed-loop operation, the calculated delta is used with the CLA duty-

output value to place event 4.

•

Events 2, 3, and 4 can be high-resolution edges.

•

Cycle-adjust A is used for period adjustment by the CPU.

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UCD3028RMHT Datasheet(PDF) 39 Page - Texas Instruments

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