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TMS570LS3137 Datasheet(PDF) 155 Page - Texas Instruments |
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TMS570LS3137 Datasheet(HTML) 155 Page - Texas Instruments |
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155 / 173 page ![]() 1 2 3 RMII_REFCLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RX_ER 6 7 11 9 8 5 4 10 5 TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 7.11.2 Ethernet RMII Electrical and Timing Specifications Figure 7-20. RMII Timing Diagram Table 7-30. Timing Requirements for EMAC RMII Receive and RMII_REFCLK NO. MIN NOM MAX UNIT 1 tc(REFCLK) Cycle time, RMII_REFCLK 20 ns 2 tw(REFCLKH) Pulse width, RMII_REFCLK high 7 13 ns 3 tw(REFCLKL) Pulse width, RMII_REFCLK low 7 13 ns 6 tsu(RXD-REFCLK) Input setup time, RMII_RXD[1:0] valid before RMII_REFCLK high 4 ns 7 th(REFCLK-RXD) Input hold time, RMII_RXD[1:0] valid after RMII_REFCLK high 2 ns 8 tsu(CRSDV-REFCLK) Input setup time, RMII_CRS_DV valid before RMII_REFCLK high 4 ns 9 th(REFCLK-CRSDV) Input hold time, RMII_CRS_DV valid after RMII_REFCLK high 2 ns 10 tsu(RXER-REFCLK) Input setup time, RMII_RX_ER valid before RMII_REFCLK high 4 ns 11 th(REFCLK-RXER) Input hold time, RMII_RX_ER valid after RMII_REFCLK high 2 ns Table 7-31. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit NO. PARAMETER MIN MAX UNIT 4 td(REFCLK-TXD) Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid 2 ns 5 td(REFCLK-TXEN) Output delay time, RMII_REFCLK high to RMII_TXEN valid 2 ns Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 155 Submit Documentation Feedback |
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