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TMS570LS3137 Datasheet(PDF) 121 Page - Texas Instruments |
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TMS570LS3137 Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 173 page  TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 7.2.3 ADC Electrical and Timing Specifications Table 7-7. MibADC Recommended Operating Conditions PARAMETER MIN MAX UNIT ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD (1) V ADREFLO A-to-D low-voltage reference source VSSAD (1) ADREFHI V VAI Analog input voltage ADREFLO ADREFHI V Analog input clamp current(2) IAIK - 2 2 mA (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) (1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4. (2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. Table 7-8. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions PARAMETER DESCRIPTION/CONDITIONS MIN MAX UNIT Analog input mux on- Rmux See Figure 7-1 250 Ω resistance ADC sample switch on- Rsamp See Figure 7-1 250 Ω resistance Cmux Input mux capacitance See Figure 7-1 16 pF Csamp ADC sample capacitance See Figure 7-1 13 pF VSSAD ≤ VIN < VSSAD + 100 mV –300 200 Analog off-state input leakage VCCAD = 3.6 V IAIL VSSAD + 100 mV ≤ VIN ≤ VCCAD - 200 mV –200 200 nA current maximum VCCAD - 200 mV < VIN ≤ VCCAD –200 500 VSSAD ≤ VIN < VSSAD + 300 mV –1000 250 Analog off-state input leakage VCCAD = 5.5 V IAIL VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV –250 250 nA current maximum VCCAD - 300 mV < VIN ≤ VCCAD –250 1000 VSSAD ≤ VIN < VSSAD + 100 mV –8 2 ADC1 Analog on-state input VCCAD = 3.6 V IAOSB1 (1) VSSAD + 100 mV < VIN < VCCAD - 200 mV –4 2 µA bias current maximum VCCAD - 200 mV < VIN < VCCAD –4 12 VSSAD ≤ VIN < VSSAD + 100 mV –7 2 ADC2 Analog on-state input VCCAD = 3.6 V IAOSB2 (1) VSSAD + 100 mV ≤ VIN ≤ VCCAD - 200 mV –4 2 µA bias current maximum VCCAD - 200 mV < VIN ≤ VCCAD –4 10 VSSAD ≤ VIN < VSSAD + 300 mV –10 3 ADC1 Analog on-state input VCCAD = 5.5 V IAOSB1 (1) VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV –5 3 µA bias current maximum VCCAD - 300 mV < VIN ≤ VCCAD –5 14 VSSAD ≤ VIN < VSSAD + 300 mV –8 3 ADC2 Analog on-state input VCCAD = 5.5 V IAOSB2 (1) VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV –5 3 µA bias current maximum VCCAD - 300 mV < VIN ≤ VCCAD –5 12 IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA Normal operating mode 15 mA ICCAD Static supply current ADC core in power down mode 5 µA (1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSL1 + IAOSL2 Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 121 Submit Documentation Feedback |
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