VT8231 datasheet(68/132 Pages) ETC

68 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-62-

Function 0 Registers - PCI to ISA Bridge

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 59 – PCS0# Control ...............................................RW

7-4

Reserved

........................................ always reads 0

PCS0# Pin Function (Pin T5)

Pin is defined as PCS0# ........................default

Pin is defined as Internal Trap I/O

2-0

Reserved

........................................ always reads 0

Offset 5A – KBC / RTC Control ......................................RW

Bits 7-4 of this register are latched from pins SD7-4 at power-

up but are read/write accessible so may be changed after

power-up to change the default strap setting:

Keyboard RP16 ............................. latched from SD7

Keyboard RP15 ............................ latched from SD6

Keyboard RP14 ............................ latched from SD5

Keyboard RP13 ............................ latched from SD4

Audio Function Enable

....... RO, strapped from SPKR pin V5

Disable (SDD pins function as SDD)

Enable (SDD pins function as Audio / Game)

Internal RTC Enable

Disable

Enable ....................................................default

Internal PS2 Mouse Enable

Disable ..................................................default

1Enable

Internal KBC Enable

Disable ..................................................default

1Enable

Note:

External strap option values may be set by connecting

the indicated external pin to a 4.7K ohm pullup (for

1) or driving it low during reset with a 7407 TTL

open collector buffer (for 0) as shown in the

suggested circuit below:

9&&

6'Q

5(6(7

9&&

Figure 5. Strap Option Circuit

Offset 5B - Internal RTC Test Mode .............................. RW

7-4

Reserved

........................................ always reads 0

Map RTC Rx32 to Rx3F

Disable................................................... default

1Enable

RTC Reset Enable (do not program)

Disable................................................... default

1Enable

RTC SRAM Access Enable

Disable................................................... default

1Enable

This bit is set if the internal RTC is disabled but it is

desired to still be able to access the internal RTC

SRAM via ports 74-75.

If the internal RTC is

enabled, setting this bit does nothing (the internal

RTC SRAM should be accessed at either ports 70/71

or 72/73.

RTC Test Mode Enable (do not program) . default=0

Offset 5C - DMA Control................................................. RW

PCS0# & PCS1# 16-Bit I/O

Disable................................................... default

1Enable

Passive Release

Disable................................................... default

1Enable

Internal Passive Release

Disable................................................... default

1Enable

Dummy PREQ

Disable................................................... default

1Enable

Reserved

........................................ always reads 0

APIC Connection

APIC on SD Bus.................................... default

APIC on XD Bus

Reserved (Do Not Program) .................... default = 0

DMA Line Buffer Disable

DMA cycles can be to/from line buffer ....... def

Disable DMA Line Buffer

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