VT8231 datasheet(19/132 Pages) ETC

19 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-13-

Pinouts

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Low Pin Count (LPC) Interface

Signal Name

Pin #

I/O

Signal Description

LFRAME#

LPC Frame.

LDRQ# / ACSDIN3 / GPI15

I / I / I

LPC Data Request.

LAD[3-0]

V7, W7, Y7, V8

IO / IO

LPC Address / Data.

HREQ1# / SD8 / GPI10

Y11

I / IO

High Priority Request 1.

HGNT1# / SD9 / GPO8

W11

O / IO

High Priority Grant 1.

HREQ2# / SD10 / GPI11

V11

I / IO

High Priority Request 2.

HGNT2# / SD11 / GPO9

T10

O / IO

High Priority Grant 2.

LREQ1# / SD12 / GPI12

U10

I / IO

Low Priority Request 1.

LGNT1# / SD13 / GPO10

Y10

O / IO

Low Priority Grant 1.

LREQ2# / SD14 / GPI13

W10

I / IO

Low Priority Request 2.

LGNT2# / SD15 / GPO11

V10

O / IO

Low Priority Grant 2.

Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

LAN Controller - Media Independent Interface (MII)

Signal Name

Pin #

I/O

Signal Description

MCOL / APICIRQ

G17

I / I

MII Collision Detect. From the external PHY.

MCRS / APICIRQ

G16

I / I

MII Carrier Sense.

Asserted by the external PHY when the

media is active.

MDCK

D17

MII Management Data Clock. Sent to the external PHY as a

timing reference for MDIO

MDIO

D18

MII Management Data I/O. Read from the MDI bit or written to

the MDO bit.

MRXCLK / APICIRQ

E17

I / I

MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.

MRXD[3],

MRXD[2],

MRXD[1],

MRXD[0] / APICIRQ

D19

D20

E18

E19

I / I

MII Receive Data.

Parallel receive data lines driven by the

external PHY synchronous with MRXCLK.

MRXDV / APICIRQ

E20

I / I

MII Receive Data Valid.

MRXERR / APICIRQ

F18

I / I

MII Receive Error. Asserted by the PHY when it detects a data

decoding error.

MTXCLK / APICIRQ

F16

I / I

MII Transmit Clock.

Always active 2.5 or 25 MHz clock

supplied by the PHY.

MTXD[3] / APICIRQ,

MTXD[2] / APICIRQ,

MTXD[1] / APICIRQ,

MTXD[0] / APICIRQ

G20

G19

G18

F20

O / I

MII Transmit Data. Parallel transmit data lines synchronized to

MTXCLK.

MTXENA / APICIRQ

F19

O / I

MII Transmit Enable. Indicates transmit active from the MII

port to the PHY.

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