GS2961 datasheet(49/104 Pages) SEMTECH

49 / 104 page

GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Data Sheet

48004 - 2

November 2009

49 of 104

4.12.1 CEA-861 Timing Generation

The GS2961 is capable of generating CEA 861 timing instead of SMPTE HVF timing for

all of the supported video formats.

This mode is selected when the TIM_861 pin is HIGH.

Horizontal sync (HSYNC), Vertical sync (VSYNC), and Data Enable (DE) timing are

output on the STAT[2:0] pins by default.

Table 4-9 shows the CEA-861 formats supported by the GS2961:

4.12.1.1 Vertical Timing

When CEA861 timing is selected, the device outputs standards compliant CEA861

timing signals as shown in the figures below; for example 240 active lines per field for

SMPTE 125M.

The register bit TRS_861 is used to select DFP timing generator mode which follows the

vertical blanking timing as defined by the embedded TRS code words. This setting is

helpful for 525i. When TRS_861 is set LOW, DE will go HIGH for 480 lines out of 525.

When TRS_861 is set HIGH, DE will go HIGH for 487 lines out of 525.

The timing of the CEA 861 timing reference signals can be found in the CEA 861

specificaitons. For information, they are included in the following diagrams. These

diagrams may not be comprehensive.

Table 4-9: Supported CEA-861 Formats

Format

CEA-861 Format

VD_STD[5:0]

720(1440) x 480i @ 59.94/60Hz

6 & 7

16h, 17h, 19h, 1Bh

720(1440) x 576i @ 50Hz

21 & 22

18h, 1Ah

1280 x 720p @ 59.94/60Hz

20h, 00h

1280 x 720p @ 50Hz

24h, 04h

1920 x 1080i @ 59.94/60Hz

2Ah, 0Ah

1920 x 1080i @ 50Hz

2Ch, 0Ch

1920 x 1080p @ 29.97/30Hz

341

2Bh, 0Bh

1920 x 1080p @ 25Hz

332

2Dh, 0Dh

1920 x 1080p @ 23.98/24Hz

30h, 10h

1920 x 1080p @ 59.94/60Hz

161

2Bh

1920 x 1080p @ 50Hz

312

2Dh

NOTES:

1,2: Timing is identical for the corresponding formats.

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