GS2961 datasheet(2/104 Pages) SEMTECH

2 / 104 page

GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Data Sheet

48004 - 2

November 2009

2 of 104

A serial digital loop-through output is provided, which can

be configured to output either reclocked or non-reclocked

serial digital data. The serial digital output can be connected

to an external cable driver.

The device operates in one of four basic modes: SMPTE

mode, DVB-ASI mode, Data-Through mode or Standby

mode.

In SMPTE mode (the default operating mode), the GS2961

performs full SMPTE processing, and features a number of

data integrity checks and measurement capabilities.

The device also supports ancillary data extraction, and can

provide entire ancillary data packets through

host-accessible registers. It also provides a variety of other

packet detection and error handling features. All of these

processing features are optional, and may be individually

enabled or disabled through register programming.

Both SMPTE 425M Level A and Level B inputs are supported

with optional conversion from Level B to Level A for 1080p

50/59.94/60 4:2:2 10-bit inputs.

In DVB-ASI mode, sync word detection, alignment and

8b/10b decoding is applied to the received data stream.

In Data-Through mode all forms of SMPTE and DVB-ASI

processing are disabled, and the device can be used as a

simple serial to parallel converter.

The device can also operate in a lower power Standby

mode. In this mode, no signal processing is carried out and

the parallel output is held static.

Parallel data outputs are provided in 20-bit or 10-bit format

for 3Gb/s, HD and SD video rates, with a variety of mapping

options. As such, this parallel bus can interface directly with

video processor ICs, and output data can be multiplexed

onto 10 bits for a low pin count interface.

Functional Block Diagram

GS2961 Functional Block Diagram

Buffer

Mux

Reclocker

with

Integrated

VCO

SDI

SDO

Serial

Parallel

Converter

Descramble,

Word Align,

Rate Detect

Flywheel

Video

Standard

Detect

TRS

Detect

Timing

Extraction

Mux

DVB-ASI

Decoder

Illegal code

remap,

TRS/

Line Number/

CRS

Insertion,

EDH Packet

Insertion

ANC/

Checksum

/352M

Extraction

GSPI and

JTAG Controller

Host

Interface

Output Mux/

Demux

Crystal

Buffer/

Oscillator

LB_CONT

VBG

I/O Control

Buffer

SDI

SMPTE 425M

1080p 50/60

4:2:2 10-bit

Level B

Level A

AGC+

AGC-

DOUT[19:0]

PCLK

LOCKED

GS2961 Datasheet(PDF) 2 Page - Semtech Corporation

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