GS2961 datasheet(28/104 Pages) SEMTECH

28 / 104 page

GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Data Sheet

48004 - 2

November 2009

28 of 104

the video data is mapped to a 20-bit virtual interface as described in SMPTE 425M. In all

cases this 20-bit parallel bus can be multiplexed onto 10 bits for a low pin count interface

with downstream devices. The associated Parallel Clock input signal operates at 148.5

or 148.5/1.001MHz (for all 3Gb/s HD 10-bit multiplexed modes), 74.25 or

74.25/1.001MHz (for HD 20-bit mode), 27MHz (for SD 10-bit mode) and 13.5MHz (for SD

20-bit mode).

Note: for 3Gb/s 10-bit mode the device operates in Dual Data Rate (DDR) mode, where

the data is sampled at both the rising and falling edges of the clock. This reduces the I/O

speed requirements of the downstream devices.

4.2 SMPTE 425M Mapping - 3G Level A and Level B Formats

4.2.1 Level A Mapping

Direct image format mapping - the mapping structure used to define 1080p/50/59.94/60

4:2:2 YCbCr 10 bit data, as supported by the GS2961. See Figure 4-1:

Figure 4-1: Level A Mapping

4.2.2 Level B Mapping

The 2 x 292 HD SDI interface - this can be two distinct links running at 1.5Gb/s or one

3Gb/s link formatted according to SMPTE 292 on two 10-bit links (Y/C interleaved). For

1080p/50/59.94/60 4:2:2 video formats, each link should be line-interleaved as per

SMPTE 372M. See Figure 4-2:

Figure 4-2: Level B Mapping

Data Stream 1

Data Stream 2

EAV

HANC

SAV

Active Video

Data Stream 1

(”Link A”)

Data Stream 2

(”Link 2”)

EAV

HANC

SAV

Active Video

“double” TRS headers from

interleaved HD-SDI;

multiplexed Y/C data

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