GS2961 datasheet(30/104 Pages) SEMTECH

30 / 104 page

GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Data Sheet

48004 - 2

November 2009

30 of 104

Figure 4-3: GS2961 Integrated EQ Block Diagram

4.4 Serial Digital Loop-Through Output

The GS2961 contains a 100Ω differential serial output buffer which can be configured to

output either a retimed or a buffered version of the serial digital input. The SDO and SDO

outputs of this buffer can interface directly to a 3Gb/s-capable, SMPTE compliant

Gennum cable driver. See 5.3 Typical Application Circuit on page 99.

When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the

serial input.

When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version

of the serial input, bypassing the internal reclocker.

The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also

disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both

SDO and SDO pins are set to VDD and remain static.

The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked

(LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’.

NOTE: the serial digital output is muted when the GS2961 is unlocked.

4.5 Serial Digital Reclocker

The GS2961 includes both a PLL stage and a sampling stage.

The PLL is comprised of two distinct loops:

Equalizer

Output

AGC

SDI

SDO

SDI

SDO

AGC

GAIN_SEL

Restore

Table 4-1: Serial Digital Output

SDO_EN/DIS

RC_BYP

SDO/SDO

Disabled

Re-timed

Buffered (not re-timed)

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