CS8952T datasheet(56/86 Pages) CIRRUS

56 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.)

BIT

NAME

TYPE

RESET

DESCRIPTION

Reserved

Read/Write 0

This bit is reserved.

Strip Preamble

Read/Write 0

When set this bit causes the 7 bytes of MAC pream-

ble to be stripped off of incoming 100 Mb/s frames.

The data received across the MII will begin with the 1

byte Start of Frame Delimiter (SFD).

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Alternate FDX CRS Read/Write 0

This bit changes the behavior of the CRS pin only in

the full-duplex (FDX) mode of operation. When set,

CRS will be asserted for transmit data only. When

clear, CRS will be asserted only for receive data.

Loopback Transmit

Disable

Read/Write 1

This bit controls whether loopback data is transmitted

onto the network. When set, any data transmitted

during PMD or ENDEC loopback mode will NOT be

transmitted onto the network. When clear, data will be

transmitted on the TX+/- pins as well as looped back

onto the MII pins.

Code Error Report

Select

Read/Write 0

When set, this bit causes code errors to be reported

by a value of 5h on RXD[3:0] and the assertion of

RX_ER.

When clear, this bit causes code errors to be reported

by a value of 6h on RXD[3:0] and the assertion of

RX_ER.

This bit is superseded by the Code Error Report

Enable bit.

CS8952T Datasheet(PDF) 56 Page - Cirrus Logic

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