CS8952T datasheet(26/86 Pages) CIRRUS

26 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

Transmission and/or reception of each byte of data

is done one nibble at a time in the following order:

MII Receive Data

The presence of recovered data on the RXD[3:0]

bus is indicated by the assertion of RX_DV.

RX_DV will remain asserted from the beginning of

the preamble (or Start of Frame Delimiter if pream-

ble is not used) to the End of Frame Delimiter.

Once RX_DV is asserted, valid data will be driven

onto RXD[3:0] synchronously with respect to

RX_CLK.

Receive errors are indicated during frame reception

by the assertion of RX_ER. It indicates that an er-

ror was detected somewhere in the frame currently

being transferred across the MII. RX_ER will tran-

sition synchronously with respect to the RX_CLK,

and will be held high for one cycle for each error

received. It is up to the MAC to ensure that a CRC

error is detected in that frame by the Logical Link

Control. Figure 2 illustrates reception without er-

rors, and Figure 3 illustrates reception with errors.

MII Transmit Data

TX_EN is used by the MAC to signal to the

CS8952T that valid nibbles of data are being pre-

sented across the MII via TXD[3:0]. TX_EN must

be asserted synchronously with the first nibble of

preamble, and must remain asserted as long as val-

id data is being presented to the MII.

TX_EN must be de-asserted within one TX_CLK

cycle after the last nibble of data (CRC) has been

presented to the CS8952T. When TX_EN is not as-

serted, data on TXD[3:0] is ignored.

MII

LSB

MSB

Nibble

Stream

MAC’s Serial Bit Stream

First Bit

First

Second

Nibble

D1 D2 D3 D4 D5 D6 D7

LSB

MSB

RX_CLK

RX_DV

RXD[3:0]

RX_ER

Preamble

SFD

Data

CRC

Figure 2. Reception without errors

RX_CLK

RX_DV

RXD[3:0]

RX_ER

Preamble

SFD

Data

Error

Figure 3. Reception with errors

CS8952T Datasheet(PDF) 26 Page - Cirrus Logic

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